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    DYNAMIC LOADLINES FOR PROGRAMMABLE FABRIC DEVICES
    1.
    发明公开
    DYNAMIC LOADLINES FOR PROGRAMMABLE FABRIC DEVICES 审中-公开

    公开(公告)号：EP4202757A1

    公开(公告)日：2023-06-28

    申请号：EP22206943.7

    申请日：2022-11-11

    申请人： INTEL Corporation

    发明人： HOSSAIN, MD ,  LI, Yuet ,  MAHESHWARI, Atul ,  NALAMALPU, Ankireddy ,  IYER, Mahesh ,  KUMASHIKAR, Mahesh

    IPC分类号： G06F30/343 ,  G06F1/26

    摘要： Systems or methods of the present disclosure may provide for determining a loadline for operation of a programmable logic fabric where the loadline is based at least in part on design configuration details for a design or a configuration rather for generic deployment of the programmable logic device. The loadline may be determined using software modeling for the design or configuration. Additionally or alternatively, the loadline may be determined using runtime testing and sensing of real-world parameters. This determination based on real-world parameters of a deployment of the configuration or design is based on a determination of a step load for the design or configuration.

    SYSTEM ENERGY EFFICIENCY IN A WIRELESS NETWORK
    4.
    发明公开
    SYSTEM ENERGY EFFICIENCY IN A WIRELESS NETWORK 审中-公开

    公开(公告)号：EP4203412A1

    公开(公告)日：2023-06-28

    申请号：EP22206653.2

    申请日：2022-11-10

    申请人： INTEL Corporation

    发明人： KUMASHIKAR, Mahesh ,  NALAMALPU, Ankireddy ,  HOSSAIN, MD ,  SUBBAREDDY, Dheeraj ,  MAHESHWARI, Atul ,  LI, Yuet ,  IYER, Mahesh

    IPC分类号： H04L41/0833 ,  H04L41/16 ,  H04L41/0823 ,  H03K19/17784 ,  H04W24/02 ,  H04W52/02

    摘要： The present disclosure relates to a device for use in a wireless network, the device including: a processor configured to: provide input data to a trained machine learning model, the input data representative of a network environment of the wireless network, wherein the trained machine learning model is configured to provide, based on the input data, output data representative of an expected performance of a plurality of configurations of network components with respect to power consumption and performance of the wireless network; select a configuration of a network component from the plurality of configurations based on the output data of the trained machine learning model; and instruct an operation of the network component according to the selected configuration; and a memory coupled with the processor, the memory storing the input data provided to the trained machine learning model and/or the output data from the trained machine learning model.

    DYNAMICALLY SCALABLE TIMING AND POWER MODELS FOR PROGRAMMABLE LOGIC DEVICES
    6.
    发明公开
    DYNAMICALLY SCALABLE TIMING AND POWER MODELS FOR PROGRAMMABLE LOGIC DEVICES 审中-公开

    公开(公告)号：EP4203320A1

    公开(公告)日：2023-06-28

    申请号：EP22207170.6

    申请日：2022-11-14

    申请人： INTEL Corporation

    发明人： MAHESHWARI, Atul ,  IYER, Mahesh ,  KUMASHIKAR, Mahesh ,  KUON, Ian ,  LI, Yuet ,  NALAMALPU, Ankireddy ,  SUBBAREDDY, Dheeraj

    IPC分类号： H03K19/177 ,  H03K19/17784 ,  G06F30/30 ,  G06F30/36

    摘要： Embodiments of the present disclosure are related to dynamically adjusting (86) a timing and/or power model for a programmable logic device. In particular, the present disclosure is directed to adjusting (86) a timing and/or power model of the programmable logic device that operates at a voltage level that is not other than a predefined voltage defined by a voltage library (82). A system (80) of the present disclosure may interpolate between voltage levels defined by the voltage libraries (82) to generate a new voltage library for the programmable logic device. A timing and/or power model (88) may be generated for the programmable logic device based on the new voltage library and the programmable logic device may be analyzed (90) using the timing and/or power model (88) at the interpolated voltage. The timing and/or power model (88) may be used to generate a bitstream (fig. 5: 106) that is used to program the integrated circuit.