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23 条记录 (耗时 0.012 秒)

    DYNAMICALLY SCALABLE TIMING AND POWER MODELS FOR PROGRAMMABLE LOGIC DEVICES
    3.
    发明公开
    DYNAMICALLY SCALABLE TIMING AND POWER MODELS FOR PROGRAMMABLE LOGIC DEVICES 审中-公开

    公开(公告)号：EP4203320A1

    公开(公告)日：2023-06-28

    申请号：EP22207170.6

    申请日：2022-11-14

    申请人： INTEL Corporation

    发明人： MAHESHWARI, Atul ,  IYER, Mahesh ,  KUMASHIKAR, Mahesh ,  KUON, Ian ,  LI, Yuet ,  NALAMALPU, Ankireddy ,  SUBBAREDDY, Dheeraj

    IPC分类号： H03K19/177 ,  H03K19/17784 ,  G06F30/30 ,  G06F30/36

    摘要： Embodiments of the present disclosure are related to dynamically adjusting (86) a timing and/or power model for a programmable logic device. In particular, the present disclosure is directed to adjusting (86) a timing and/or power model of the programmable logic device that operates at a voltage level that is not other than a predefined voltage defined by a voltage library (82). A system (80) of the present disclosure may interpolate between voltage levels defined by the voltage libraries (82) to generate a new voltage library for the programmable logic device. A timing and/or power model (88) may be generated for the programmable logic device based on the new voltage library and the programmable logic device may be analyzed (90) using the timing and/or power model (88) at the interpolated voltage. The timing and/or power model (88) may be used to generate a bitstream (fig. 5: 106) that is used to program the integrated circuit.

    METHOD FOR MACHINE LEARNING A DETECTION OF AT LEAST ONE IRREGULARITY IN A PLASMA SYSTEM
    5.
    发明公开
    METHOD FOR MACHINE LEARNING A DETECTION OF AT LEAST ONE IRREGULARITY IN A PLASMA SYSTEM 审中-公开

    公开(公告)号：EP4242904A2

    公开(公告)日：2023-09-13

    申请号：EP23184108.1

    申请日：2021-10-06

    申请人： Comet AG

    发明人： vor dem Brocke, Manuel ,  Schlierf, Roland ,  Grede, André ,  Gruner, Daniel ,  Schwerg, Nikolai ,  Labanc, Anton ,  Fink, Thomas

    IPC分类号： G06F30/36

    摘要： The invention relates to a method for machine learning a detection of at least one irregularity in a plasma system, particularly an RF powered plasma processing system, comprising:
    - Providing at least one input signal (210) each related to an analog signal of a power delivery system (1) for the plasma system and/or to another characteristic of the power delivery system (1) and/or of the plasma system, the at least one input signal (210) having at least one irregularity feature indicative of the irregularity in the plasma system,
    - Performing a machine learning procedure (310) wherein the at least one input signal (210) having the at least one irregularity feature is processed by a programmable circuit (10) to train the detection of the irregularity in the plasma system.

    PROGRAMMABLE ANALOG SIGNAL PROCESSING ARRAY FOR TIME-DISCRETE PROCESSING OF ANALOG SIGNALS
    6.
    发明公开
    PROGRAMMABLE ANALOG SIGNAL PROCESSING ARRAY FOR TIME-DISCRETE PROCESSING OF ANALOG SIGNALS 审中-公开

    公开(公告)号：EP4024265A1

    公开(公告)日：2022-07-06

    申请号：EP21176328.9

    申请日：2021-05-27

    申请人： IHP GmbH - Innovations for High Performance Microelectronics / Leibniz-Institut für innovative Mikroelektronik

    发明人： Kahmen, Gerhard ,  Grass, Eckhard

    IPC分类号： G06G7/26 ,  G06G7/06 ,  G06G7/625 ,  G06F30/34 ,  G06F30/36

    摘要： A programmable analog processing array for programmable time-discrete processing of analog input signals in accordance with a desired signal processing function comprises a network of mutually interconnectable and pre-configurable analog processing slices that form unit circuit cells of the network. Each processing slice comprises a set of cell circuit elements including: a switchable clock input port for receiving a clock signal, a delay element for receiving a respective analog slice input signal and for forwarding the received slice input signal with a pre-configurable time delay as a respective delayed slice input signal, an analog multiplier element receiving the delayed slice input signal for providing an analog multiplier output signal corresponding to a product of the delayed slice input signal with a pre-configurable multiplication factor, an analog adder element receiving a pre-configurable selection of at least two adder input signals including the multiplier output signal and for providing an analog adder output signal corresponding to a sum of the adder input signals, and including an analog resample element for receiving the adder output signal and for providing the received adder output with a pre-configurable time delay as an analog slice output signal.