公开(公告)号：EP3832474A1

公开(公告)日：2021-06-09

申请号：EP20196158.8

申请日：2020-09-15

申请人： INTEL Corporation

发明人： Blankenship, Robert G. ,  Choudhary, Swadesh ,  Abraham, Vinit Mathew ,  Liu, Yen-Cheng ,  Kumar, Sailesh ,  Gadey, Siva Prasad

IPC分类号： G06F13/42 ,  G06F12/0806

摘要： An interface for coupling an agent to a fabric supports a set of coherent interconnect protocols and includes a global channel to communicate control signals to support the interface, a request channel to communicate messages associated with requests to other agents on the fabric, a response channel to communicate responses to other agents on the fabric, and a data channel to couple to communicate messages associated with data transfers to other agents on the fabric, where the data transfers include payload data.

公开(公告)号：EP4394598A1

公开(公告)日：2024-07-03

申请号：EP23198126.7

申请日：2023-09-19

申请人： Intel Corporation

发明人： Herdrich, Andrew J. ,  Abraham, Philip ,  Autee, Priya ,  Van Doren, Stephen ,  Liu, Yen-Cheng ,  Sankaran, Rajesh ,  Subramaniam, Kameswar ,  Parikh, Ritesh

IPC分类号： G06F9/50 ,  G06F11/30

CPC分类号： G06F9/5016 ,  G06F2201/88520130101 ,  G06F12/00 ,  G06F11/3409

摘要： Techniques for region-aware memory bandwidth allocation control are described. In an embodiment, an apparatus includes a processing core and control circuitry. The processing core is to execute a plurality of threads. The control circuitry is to control use of memory bandwidth per memory region and per thread.

公开(公告)号：EP4170507A1

公开(公告)日：2023-04-26

申请号：EP22209604.2

申请日：2020-09-15

申请人： INTEL Corporation

发明人： Blankenship, Robert G. ,  Choudhary, Swadesh ,  Mathew Abraham, Vinit ,  Liu, Yen-Cheng ,  Kumar, Sailesh ,  Gadey, Siva Prasad

IPC分类号： G06F13/42 ,  G06F12/0806

摘要： This disclosure pertains to point-to-point interconnects. For example, an apparatus comprises a fabric block including circuitry to support a plurality of coherent protocols, an agent block including circuitry to support at least one of the plurality of coherent protocols from the fabric block and an interface between the fabric block and the agent block. The interface includes a request physical channel to carry address and protocol level command information associated with requests from the agent block or the fabric block, a response physical channel to carry responses to the requests from the agent block or the fabric block, a data physical channel to carry data transfers from the agent block or the fabric block, and a global physical channel to carry global control signals that apply to the request physical channel, the response physical channel, and the data physical channel.

公开(公告)号：EP4198744A1

公开(公告)日：2023-06-21

申请号：EP22207686.1

申请日：2022-11-16

申请人： Intel Corporation

发明人： Agarwal, Monam ,  Enamandram, Anand K. ,  Chen, Wei ,  Vander Kamp, Kerry ,  Branch, Robert A. ,  Liu, Yen-Cheng

IPC分类号： G06F12/02 ,  G06F12/06

摘要： Techniques and mechanisms for identifying a memory access resource which is to be a target of an access request. In an embodiment, a processor comprises route tables which are to provide entries corresponding to different respective memory access resources which are coupled to the processor. The processor further comprises a list of items which each correspond to a different respective range of addresses, wherein the items each include an identifier of a respective route table, and an identifier of a respective index offset. Based on an address of the access request, a decoder circuit of the processor searches the list to identify a corresponding one of the items. In another embodiment, the decoder circuit accesses a route table entry, based on the search, to determine how the access request is to be directed to a particular memory access resource.

公开(公告)号：EP4155947A1

公开(公告)日：2023-03-29

申请号：EP22184591.0

申请日：2022-07-13

申请人： INTEL Corporation

发明人： Zhang, Yongmei ,  Hilewitz, Yedidya ,  Liu, Yen-Cheng

IPC分类号： G06F12/0831 ,  G06F12/121

摘要： In an embodiment, a processor may include an execution engine to execute a plurality of instructions, a memory to store a tagged data structure comprising a plurality of entries, and an eviction circuit. The eviction circuit may be to: generate a pseudo-random number responsive to an eviction request for the tagged data structure; in response to a determination that the pseudo-random number is outside of a valid eviction range for the plurality of entries, generate an alternative identifier by rotating through the valid eviction range, the valid eviction range comprising a range of numbers that are valid to identify victim entries of the tagged data structure; and evict a victim entry from the tagged data structure, the victim entry associated with the alternative identifier. Other embodiments are described and claimed.

公开(公告)号：EP3866020A1

公开(公告)日：2021-08-18

申请号：EP21165826.5

申请日：2020-09-15

申请人： INTEL Corporation

发明人： Blankenship, Robert G. ,  Choudhary, Swadesh ,  Abraham, Vinit Mathew ,  Liu, Yen-Cheng ,  Kumar, Sailesh ,  Gadey, Siva Prasad

IPC分类号： G06F13/42 ,  G06F12/0806

摘要： This disclosure pertains to point-to-point interconnects. In particular, an apparatus comprising an agent block comprising circuitry to support a plurality of coherent protocols, is provided. The agent block comprises an interface to communicate with a fabric. The interface comprises: a global channel to use a first set of wires, wherein the global channel is to carry signals for initialization of the interface; a request channel to use a second set of wires, wherein the request channel is to carry address and protocol level command information associated with requests sent from the agent block; a response channel to use a third set of wires, wherein the response channel is to carry responses to the requests sent from the agent block; and a data channel to use a fourth set of wires, wherein the data channel is to carry data transfers from the agent block to other agents via the fabric.