公开(公告)号：EP4202776A1

公开(公告)日：2023-06-28

申请号：EP22206930.4

申请日：2022-11-11

申请人： INTEL Corporation

发明人： LANGHAMMER, Martin ,  TUNALI, Nihat ,  WU, Michael

IPC分类号： G06N3/063 ,  G06N3/0464 ,  G06F7/544 ,  G06N3/10

摘要： This disclosure is directed to a digital signal processing (DSP) block that includes multiple weight registers configurable to receive and store a first plurality of values having multiple precisions, and multiple multipliers that are each configurable to receive a respective value of the first plurality of values. The DSP block further includes one or more inputs configurable to receive a second plurality of values, and a multiplexer network configurable to receive the second plurality of values and route each respective value of the second plurality of values to a multiplier of the multipliers. The multipliers are configurable to simultaneously multiply each value of the first plurality of values by a respective value of the second plurality of values to generate a plurality of products. Additionally, the DSP block includes adder circuitry configurable to generate a first sum and a second sum based on the plurality of products.

公开(公告)号：EP4155901A1

公开(公告)日：2023-03-29

申请号：EP22189009.8

申请日：2022-08-05

申请人： INTEL Corporation

发明人： GANUSOV, Ilya ,  LANGHAMMER, Martin ,  TUNALI, Nihat ,  WU, Michael

IPC分类号： G06F7/544

摘要： This disclosure is directed to a digital signal processing (DSP) block that includes multiple weight registers configurable to receive and store a first plurality of values, and multiple multipliers that are each configurable to receive a respective value of the first plurality of values. The DSP block further includes one or more inputs configurable to receive a second plurality of values, and a multiplexer network configurable to receive the second plurality of values and route each respective value of the second plurality of values to a multiplier of the multipliers. The multipliers are configurable to simultaneously multiply each value of the first plurality of values by a respective value of the second plurality of values to generate a plurality of products. Additionally, the DSP block includes adder circuitry configurable to generate a first sum and a second sum based on the plurality of products.