公开(公告)号：EP4359907A1

公开(公告)日：2024-05-01

申请号：EP22828941.9

申请日：2022-03-25

申请人： INTEL Corporation

发明人： LANGHAMMER, Martin

IPC分类号： G06F7/523 ,  G06F8/41 ,  G06F7/50

CPC分类号： G06F7/5443 ,  G06F8/41

公开(公告)号：EP3457571A3

公开(公告)日：2019-05-29

申请号：EP18187147.6

申请日：2018-08-02

申请人： INTEL Corporation

发明人： LANGHAMMER, Martin ,  PASCA, Bogdan

IPC分类号： H03K19/177

摘要： An integrated circuit may include a floating-point adder. The adder may be implemented using a dual-path adder architecture having a near path and a far path. The near path may include a leading zero anticipator (LZA), a comparison circuit for comparing an exponent value to an LZA count, and associated circuitry for handling subnormal numbers. The far path may include a subtraction circuit for computing the difference between a received exponent value and a minimum exponent value, at least two shifters for shifting far greater and far lesser mantissa values in parallel, and associated circuitry for handling subnormal numbers. The adder may be dynamically configured to support a first mode that processes FP16 at inputs and outputs, a second mode that processes modified FP16' inputs, and a third mode that processes FP16' at inputs and outputs.

公开(公告)号：EP3457571A2

公开(公告)日：2019-03-20

申请号：EP18187147.6

申请日：2018-08-02

申请人： INTEL Corporation

发明人： LANGHAMMER, Martin ,  PASCA, Bogdan

IPC分类号： H03K19/177

摘要： An integrated circuit may include a floating-point adder. The adder may be implemented using a dual-path adder architecture having a near path and a far path. The near path may include a leading zero anticipator (LZA), a comparison circuit for comparing an exponent value to an LZA count, and associated circuitry for handling subnormal numbers. The far path may include a subtraction circuit for computing the difference between a received exponent value and a minimum exponent value, at least two shifters for shifting far greater and far lesser mantissa values in parallel, and associated circuitry for handling subnormal numbers. The adder may be dynamically configured to support a first mode that processes FP16 at inputs and outputs, a second mode that processes modified FP16' inputs, and a third mode that processes FP16' at inputs and outputs.

公开(公告)号：EP3418884A1

公开(公告)日：2018-12-26

申请号：EP18171363.7

申请日：2018-05-08

申请人： INTEL Corporation

发明人： LANGHAMMER, Martin ,  BAECKLER, Gregg

IPC分类号： G06F7/533

CPC分类号： G06F7/523 ,  G06F7/4824 ,  G06F7/5336 ,  G06F2207/4812

摘要： Systems, methods, and devices for enhancing performance/efficiency of soft multiplier implementations are provided. More specifically, a method to implement soft multipliers with a high radix subset code architecture is provided. The techniques provided herein result in smaller multipliers that consume less area, improve packing, consume less power, and improve routing options on an integrated circuit.

公开(公告)号：EP4202776A1

公开(公告)日：2023-06-28

申请号：EP22206930.4

申请日：2022-11-11

申请人： INTEL Corporation

发明人： LANGHAMMER, Martin ,  TUNALI, Nihat ,  WU, Michael

IPC分类号： G06N3/063 ,  G06N3/0464 ,  G06F7/544 ,  G06N3/10

摘要： This disclosure is directed to a digital signal processing (DSP) block that includes multiple weight registers configurable to receive and store a first plurality of values having multiple precisions, and multiple multipliers that are each configurable to receive a respective value of the first plurality of values. The DSP block further includes one or more inputs configurable to receive a second plurality of values, and a multiplexer network configurable to receive the second plurality of values and route each respective value of the second plurality of values to a multiplier of the multipliers. The multipliers are configurable to simultaneously multiply each value of the first plurality of values by a respective value of the second plurality of values to generate a plurality of products. Additionally, the DSP block includes adder circuitry configurable to generate a first sum and a second sum based on the plurality of products.

公开(公告)号：EP4109235A1

公开(公告)日：2022-12-28

申请号：EP22163524.6

申请日：2022-03-22

申请人： INTEL Corporation

发明人： LANGHAMMER, Martin

IPC分类号： G06F7/483 ,  G06F7/544

摘要： A digital signal processing (DSP) block includes a plurality of multipliers and a summation block separate from the plurality of multipliers. The DSP block is configurable to perform a first multiplication operation to determine a first product of a first floating-point value and a second floating-point value using only a first multiplier of the plurality of multipliers. Additionally, the DSP block is configurable to perform a second multiplication operation between a third floating-point value and a fourth floating-point value by receiving, at each of the plurality of multipliers, two integer values generated from the third floating-point value and the fourth floating-point value, generating, via the plurality of multipliers, a plurality of subproducts by multiplying, at each of the multipliers, the two integer values, and generating a second product of the second multiplication operation by adding, via the summation block, the plurality of subproducts.

公开(公告)号：EP4202641A1

公开(公告)日：2023-06-28

申请号：EP22206934.6

申请日：2022-11-11

申请人： INTEL Corporation

发明人： MENON, Sankaran ,  SIMHA, Kuldeep ,  LANGHAMMER, Martin ,  FANASWALLA, Mustansir

IPC分类号： G06F7/57 ,  H03K19/177

摘要： An integrated circuit is provided that includes via-configured structured logic circuitry and an embedded arithmetic block that interfaces with the via-configured structured logic circuitry to perform an arithmetic function. The embedded arithmetic block includes at least one monolithic arithmetic circuit that can perform the arithmetic function more efficiently or taking up less die space than a comparable circuit formed from the via-configured structured logic circuitry.

公开(公告)号：EP4109236A1

公开(公告)日：2022-12-28

申请号：EP22164550.0

申请日：2022-03-25

申请人： INTEL Corporation

发明人： KRISHNAMURTHY, Ram ,  ANDERS, Mark ,  KAUL, Himanshu ,  CHINYA, Gautham ,  POWER, Martin ,  MOHAPATRA, Debabrata ,  RAHA, Arnab ,  LANGHAMMER, Martin ,  BRICK, Cormac

IPC分类号： G06F7/53

摘要： Systems, apparatuses and methods may provide for multi-precision multiply-accumulate (MAC) technology that includes a plurality of arithmetic blocks, wherein the plurality of arithmetic blocks each contain multiple multipliers, and wherein the logic is to combine multipliers one or more of within each arithmetic block or across multiple arithmetic blocks. In one example, one or more intermediate multipliers are of a size that is less than precisions supported by arithmetic blocks containing the one or more intermediate multipliers.

公开(公告)号：EP4155901A1

公开(公告)日：2023-03-29

申请号：EP22189009.8

申请日：2022-08-05

申请人： INTEL Corporation

发明人： GANUSOV, Ilya ,  LANGHAMMER, Martin ,  TUNALI, Nihat ,  WU, Michael

IPC分类号： G06F7/544

摘要： This disclosure is directed to a digital signal processing (DSP) block that includes multiple weight registers configurable to receive and store a first plurality of values, and multiple multipliers that are each configurable to receive a respective value of the first plurality of values. The DSP block further includes one or more inputs configurable to receive a second plurality of values, and a multiplexer network configurable to receive the second plurality of values and route each respective value of the second plurality of values to a multiplier of the multipliers. The multipliers are configurable to simultaneously multiply each value of the first plurality of values by a respective value of the second plurality of values to generate a plurality of products. Additionally, the DSP block includes adder circuitry configurable to generate a first sum and a second sum based on the plurality of products.

公开(公告)号：EP4350990A1

公开(公告)日：2024-04-10

申请号：EP23185773.1

申请日：2023-07-17

申请人： INTEL Corporation

发明人： LANGHAMMER, Martin

IPC分类号： H03H17/02 ,  H03H17/06

摘要： Integrated circuit devices, methods, and circuitry for implementing and using a flexible circuit for real and complex filter operations are provided. An integrated circuit may include programmable logic circuitry and digital signal processor (DSP) blocks. The DSP blocks may be configurable to receive inputs from the programmable logic circuitry and may include first and second multiplier pairs. The first multiplier pair may include a first multiplier that may receive a first input and a second input and a second multiplier that may receive the second input and a third input of the inputs. The second multiplier pair may include a third multiplier that may receive the first input or a fourth input and a fifth input and a fourth multiplier that may receive the third input or a fifth input and a sixth input.