公开(公告)号：EP4394875A1

公开(公告)日：2024-07-03

申请号：EP23200865.6

申请日：2023-09-29

申请人： INTEL Corporation

发明人： WEI, Andy Chih-Hung ,  KE, Po-Yao ,  KAU, Derchang

IPC分类号： H01L27/02 ,  H01L27/06

CPC分类号： H01L27/0255 ,  H01L27/0296 ,  H01L27/0688 ,  H01L27/0635 ,  H01L27/0647

摘要： Structures having stacked electrostatic discharge (ESD) for backside power delivery are described. In an example, an integrated circuit structure includes a device layer having a front side opposite a backside. A front side metallization layer is above the front side of the device layer. A silicon substrate is above the front side metallization layer. The silicon substrate has a diode and/or a bipolar junction transistor therein. The diode and/or bipolar junction transistor is coupled to the device layer through the front side metallization layer by one or more conductive structures. A backside metallization layer is below the backside of the device layer.

公开(公告)号：EP4202999A2

公开(公告)日：2023-06-28

申请号：EP22214741.5

申请日：2022-12-19

申请人： INTEL Corporation

发明人： LAVRIC, Dan S. ,  CHIU, YenTing ,  HARAN, Mohit K. ,  GARDINER, Allen B. ,  GULER, Leonard P. ,  WEI, Andy Chih-Hung ,  GHANI, Tahir

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

摘要： Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to integrated circuits with self-aligned tub architectures.

公开(公告)号：EP4199066A1

公开(公告)日：2023-06-21

申请号：EP22213216.9

申请日：2022-12-13

申请人： INTEL Corporation

发明人： BOUCHE, Guillaume ,  NAVABI-SHIRAZI, Aryan ,  WEI, Andy Chih-Hung ,  KOBRINSKY, Mauro ,  MILLS, Shaun ,  PATEL, Pratik

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775

摘要： Gate-all-around integrated circuit structures having backside contact self-aligned to epitaxial source or drain region are described. An integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures (268A) are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures (268B) are at ends of the second vertical arrangement of nanowires. A conductive structure (262) is vertically beneath and in contact with one of the first epitaxial source or drain structures (268A).

公开(公告)号：EP4123690A2

公开(公告)日：2023-01-25

申请号：EP22180477.6

申请日：2022-06-22

申请人： INTEL Corporation

发明人： WEI, Andy Chih-Hung ,  BOUCHE, Guillaume

IPC分类号： H01L21/74 ,  H01L21/8238 ,  H01L23/528 ,  H01L23/535 ,  H01L21/768

摘要： Embodiments described herein may be related to apparatuses, processes, and techniques related to a transistor structure that includes a buried power rail (BPR) located within the transistor structure at a level below a height of one or more of the fins of the transistor structure. The BPR may be located proximate to a bottom substrate of the transistor structure. In embodiments, the transistor structure includes a protective layer, which can include one or more dielectric layers, above the BPR to protect the BPR during stages of transistor structure manufacture. In embodiments, portions of the protective layer may also be used to constrain epitaxial growth during stages of manufacturing of the transistor structure. Other embodiments may be described and/or claimed.

公开(公告)号：EP4109523A1

公开(公告)日：2022-12-28

申请号：EP22169729.5

申请日：2022-04-25

申请人： INTEL Corporation

发明人： PARK, Changyok ,  WEI, Andy Chih-Hung

IPC分类号： H01L23/535 ,  H01L23/528 ,  H01L21/74 ,  H01L27/092 ,  H01L21/8238 ,  H01L23/48 ,  H01L21/768

摘要： Embodiments described herein may be related to apparatuses, processes, and techniques related to well biasing using a buried power rail (BPR) within a circuit structure. Embodiments include using a silicide material between the BPR and a well, where the silicide material provides ohmic contact between the BPR and the well. Other embodiments may be described and/or claimed.

公开(公告)号：EP4202999A3

公开(公告)日：2023-11-22

申请号：EP22214741.5

申请日：2022-12-19

申请人： INTEL Corporation

发明人： LAVRIC, Dan S. ,  CHIU, YenTing ,  HARAN, Mohit K. ,  GARDINER, Allen B. ,  GULER, Leonard P. ,  WEI, Andy Chih-Hung ,  GHANI, Tahir

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

摘要： Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to integrated circuits with self-aligned tub architectures.

公开(公告)号：EP4195250A1

公开(公告)日：2023-06-14

申请号：EP22206493.3

申请日：2022-11-09

申请人： INTEL Corporation

发明人： GHANI, Tahir ,  WALLACE, Charles ,  GULER, Leonard ,  HARAN, Mohit ,  YEMENICIOGLU, Sukru ,  WEI, Andy Chih-Hung

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

摘要： A structure includes a first vertical stack of horizontal nanowires having a first width. A second vertical stack of horizontal nanowires is spaced apart from and parallel with the first vertical stack of horizontal nanowires and has the first width. A first gate structure includes a first gate structure portion over the first vertical stack of horizontal nanowires, a second gate structure portion over the second vertical stack of horizontal nanowires, and a gate cut between the first gate structure portion and the second gate structure portion. A third vertical stack of horizontal nanowires has a second width greater than the first width. A fourth vertical stack of horizontal nanowires is spaced apart from and parallel with the third vertical stack of horizontal nanowires and has the second width. A second gate structure is continuous over the third vertical stack of horizontal nanowires and over the fourth vertical stack of horizontal nanowires.

公开(公告)号：EP4109503A1

公开(公告)日：2022-12-28

申请号：EP22164186.3

申请日：2022-03-24

申请人： INTEL Corporation

发明人： WEI, Andy Chih-Hung

IPC分类号： H01L21/768 ,  H01L23/485 ,  H01L23/522

摘要： Embodiments described herein may be related to apparatuses, processes, and techniques related to construct via gate contact (VCG) between a metal gate of a gate structure and a metallization layer, where the VCG is split into two separate portions. The bottom portion may be oversized with respect to the metal gate and self-aligned to a trench connector in a same layer as the bottom portion of the VCG. The top portion may be an inverse taper that may be used to electrically couple the bottom portion of the VCG with the metallization layer to reduce the effects of edge placement error. Other embodiments may be described and/or claimed.

公开(公告)号：EP4064333A1

公开(公告)日：2022-09-28

申请号：EP22157125.0

申请日：2022-02-16

申请人： Intel Corporation

发明人： WEI, Andy Chih-Hung

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L21/74 ,  H01L23/528

摘要： An example IC structure includes a plurality of elongated channel structures (e.g., fins or nanoribbons) and one or more metal gate lines crossing over the fins/nanoribbons. A buried power rail (BPR) is formed between a pair of adjacent fins/nanoribbons. Once a BPR has been formed, an opening (310) is formed above the BPR. The opening has an elongated shape that extends horizontally along the length of the BPR and extends vertically from the top of the BPR to the top of the IC structure, cutting through the metal gate lines. Portions of the opening between cut portions of metal gate lines may be filled with a dielectric material, thus forming metal gate cuts. A portion of the opening that is not between cut portions of a metal gate line is filled with an electrically conductive material and coupled to a source/drain contact of a transistor, thus forming a conductive via.

公开(公告)号：EP4020589A1

公开(公告)日：2022-06-29

申请号：EP21198750.8

申请日：2021-09-24

申请人： INTEL Corporation

发明人： KAVALIEROS, Jack ,  BOUCHE, Guillaume ,  WEI, Andy Chih-Hung

IPC分类号： H01L29/775 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/78 ,  H01L27/092 ,  H01L21/02 ,  H01L21/336 ,  B82Y10/00

摘要： Gate-all-around integrated circuit structures having germanium-diffused nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium-diffused nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a sub-fin structure, wherein individual ones of the vertical arrangement of nanowires include silicon and germanium, and wherein the sub-fin structure has a relatively higher germanium concentration at a top of the sub-fin structure than at a bottom of the sub-fin structure.