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公开(公告)号：EP4152160A1
公开(公告)日：2023-03-22
申请号：EP22188320.0
申请日：2022-08-02
申请人： INTEL Corporation
发明人： WILLHALM, Thomas , GUIM BERNAT, Francesc , KUMAR, Karthik , GUPTA, Rita , SCHMISSEUR, Mark , ZIAKAS, Dimitrios
摘要： An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller to allocate a first secure portion of a pooled memory to a first instantiation of an application on a first node, and circuitry coupled to the one or more substrates and the controller, the circuitry to provide a failover interface for a second instantiation of the application on a second node to access the first secure portion of the pooled memory in the event of a failure of the first node. Other embodiments are disclosed and claimed.
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2.发明公开
公开(公告)号：EP4128710A1
公开(公告)日：2023-02-08
申请号：EP20927615.3
申请日：2020-12-11
申请人： INTEL Corporation
发明人： GUIM BERNAT, Francesc , PUTYRSKI, Slawomir , BALLE, Susanne, M. , WILLHALM, Thomas , KUMAR, Karthik
IPC分类号： H04L29/08 , H04L12/911
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公开(公告)号：EP3474149A1
公开(公告)日：2019-04-24
申请号：EP18191339.3
申请日：2018-08-28
申请人： INTEL Corporation
IPC分类号： G06F13/00
摘要： Examples may include a data center in which memory sleds are provided with logic to filter data stored on the memory sled responsive to filtering requests from a compute sled. Memory sleds may include memory filtering logic arranged to receive filtering requests, filter data stored on the memory sled, and provide filtering results to the requesting entity. Additionally, a data center is provided in which fabric interconnect protocols in which sleds in the data center communicate is provided with filtering instructions such that compute sleds can request filtering on memory sleds.
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公开(公告)号：EP3460662A1
公开(公告)日：2019-03-27
申请号：EP18191343.5
申请日：2018-08-28
申请人： INTEL Corporation
IPC分类号： G06F9/50
摘要： Technologies for offloading I/O intensive workload phases to a data storage sled include a compute sled. The compute sled is to execute a workload that includes multiple phases. Each phase is indicative of a different resource utilization over a time period. Additionally, the compute sled is to identify an I/O intensive phase of the workload, wherein the amount of data to be communicated through a network path between the compute sled and the data storage sled to execute the I/O intensive phase satisfies a predefined threshold. The compute sled is also to migrate the workload to the data storage sled to execute the I/O intensive phase locally on the data storage sled. Other embodiments as also described and claimed.
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公开(公告)号：EP3506107A1
公开(公告)日：2019-07-03
申请号：EP18208737.9
申请日：2018-11-27
申请人： INTEL Corporation
摘要： Technology for a memory controller is described. The memory controller can receive a request to store training data. The request can include a model identifier (ID) that identifies a model that is associated with the training data. The memory controller can send a write request to store the training data associated with the model ID in a memory region in a pooled memory that is allocated for the model ID. The training data that is stored in the memory region in the pooled memory can be addressable based on the model ID.
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公开(公告)号：EP3462327A3
公开(公告)日：2019-04-24
申请号：EP18191576.0
申请日：2018-08-29
申请人： INTEL Corporation
IPC分类号： G06F13/16
摘要： A memory controller method and apparatus, which includes a modification of at least one of a first timing scheme or a second timing scheme based on information about one or more data requests to be included in at least one of a first queue scheduler or a second queue scheduler, the first timing scheme indicating when one or more requests in the first queue scheduler are to be issued to the first memory set via a first memory set interface and over a channel, the second timing scheme indicating when one or more requests in the second queue scheduler are to be issued to the second memory set via a second memory set interface and over the channel. Furthermore, an issuance of a request to at least one of the first memory set in accordance with the modified first timing scheme or the second memory set in accordance with the modified second timing scheme may be included.
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公开(公告)号：EP3436920A1
公开(公告)日：2019-02-06
申请号：EP16897340.2
申请日：2016-03-31
申请人： INTEL Corporation
发明人： GUIM BERNAT, Francesc , WILLHALM, Thomas , KUMAR, Karthik , DIMITROV, Martin P. , RAMANUJAN, Raj K.
IPC分类号： G06F3/06
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公开(公告)号：EP3274838A1
公开(公告)日：2018-01-31
申请号：EP16773660.2
申请日：2016-02-25
申请人： Intel Corporation
CPC分类号： G06F11/3688 , G06F11/3648 , G06F11/3664
摘要： Technologies for software testing include a computing device having persistent memory that includes a platform simulator and an application or other code module to be tested. The computing device generates a checkpoint for the application at a test location using the platform simulator. The computing device executes the application from the test location to an end location and traces all writes to persistent memory using the platform simulator. The computing device generates permutations of persistent memory writes that are allowed by the hardware specification of the computing device simulated by the platform simulator. The computing device replays each permutation from the checkpoint, simulates a power failure, and then invokes a user-defined test function using the platform simulator. The computing device may test different permutations of memory writes until the application's use of persistent memory is validated. Other embodiments are described and claimed.
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公开(公告)号：EP3506116A1
公开(公告)日：2019-07-03
申请号：EP18209302.1
申请日：2018-11-29
申请人： INTEL Corporation
摘要： Technology for a memory controller is described. The memory controller can receive a request from a data consumer node in a data center for training data. The training data indicated in the request can correspond to a model identifier (ID) of a model that runs on the data consumer node. The memory controller can identify a data provider node in the data center that stores the training data that is requested by the data consumer node. The data provider node can be identified using a tracking table that is maintained at the memory controller. The memory controller can send an instruction to the data provider node that instructs the data provider node to send the training data to the data consumer node to enable training of the model that runs on the data consumer node.
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