公开(公告)号：EP3982273A1

公开(公告)日：2022-04-13

申请号：EP21211326.0

申请日：2018-07-30

申请人： INTEL Corporation

发明人： BERNAT, Francesc Guim ,  BALLE, Susanne M. ,  PUTYRSKI, Slawomir ,  KHANNA, Rahul ,  DORMITZER, Paul

IPC分类号： G06F15/78 ,  G06F9/54 ,  G06F9/50

摘要： Technologies for pre-configuring accelerators by predicting bit-streams include communication circuitry and a compute device. The compute device includes a compute engine to determine one or more bit-streams registered on each accelerator of multiple accelerators. The compute engine is further to predict a next job to be requested for acceleration from an application of at least one compute sled of multiple compute sleds, predict a bit-stream from a bit-stream library that is to execute the predicted next job requested to be accelerated, and determine whether the predicted bit-stream is already registered on one of the accelerators. In response to a determination that the predicted bit-stream is not registered on one of the accelerators, the compute engine is to select an accelerator from the plurality of accelerators that satisfies characteristics of the predicted bit-stream and register the predicted bit-stream on the determined accelerator.

公开(公告)号：EP3454530A1

公开(公告)日：2019-03-13

申请号：EP18191345.0

申请日：2018-08-28

申请人： Intel Corporation

发明人： BERNAT, Francesc Guim ,  CUSTODIO, Evan ,  BALLE, Susanne M. ,  GRECCO, Joe ,  MITCHEL, Henry ,  KHANNA, Rahul ,  PUTYRSKI, Slawomir ,  SEN, Sujoy ,  DORMITZER, Paul

IPC分类号： H04L29/08 ,  H04L12/861 ,  H04L29/06 ,  G06F9/50 ,  G06F17/50

摘要： Technologies for providing accelerated functions as a service in a disaggregated architecture include a compute device that is to receive a request for an accelerated task. The task is associated with a kernel usable by an accelerator sled communicatively coupled to the compute device to execute the task. The compute device is further to determine, in response to the request and with a database indicative of kernels and associated accelerator sleds, an accelerator sled that includes an accelerator device configured with the kernel associated with the request. Additionally, the compute device is to assign the task to the determined accelerator sled for execution. Other embodiments are also described and claimed.

公开(公告)号：EP3422188A1

公开(公告)日：2019-01-02

申请号：EP18175273.4

申请日：2018-05-30

申请人： INTEL Corporation

发明人： DOSHI, Kshitij A. ,  BERNAT, Francesc Guim ,  SCHMISSEUR, Mark A.

IPC分类号： G06F11/30 ,  G06F11/34

摘要： Technologies for producing proactive notifications of data storage performance include a compute device. The compute device is to obtain key indicator data indicative of a performance condition associated with operations of one or more data storage devices and an associated predefined threshold that, if satisfied, indicates the presence of a key indicator. The compute device is also to obtain remedial action data indicative of a remedial action to be performed by the compute device in response to identification of the key indicator in telemetry data produced by the compute device during operation, analyze the telemetry data to determine whether the key indicator is present in the telemetry data, perform, in response to a determination that the key indicator is present, the predefined remedial action, and send a notification of the predefined indicator to a remote compute device.

公开(公告)号：EP3823245A1

公开(公告)日：2021-05-19

申请号：EP20217841.4

申请日：2018-08-28

申请人： INTEL Corporation

发明人： BERNAT, Francesc Guim ,  CUSTODIO, Evan ,  BALLE, Susanne M. ,  GRECCO, Joe ,  MITCHEL, Henry ,  KHANNA, Rahul ,  PUTYRSKI, Slawomir ,  SEN, Sujoy ,  DORMITZER, Paul

IPC分类号： H04L29/06

摘要： Network switch circuitry for use with a physical network infrastructure is provided that supports multiple different link-layer protocols and that provides telemetry information related to the network switch circuitry. A method and a machine-readable storage medium are also provided.

公开(公告)号：EP3460673A1

公开(公告)日：2019-03-27

申请号：EP18186430.7

申请日：2018-07-30

申请人： INTEL Corporation

发明人： CUSTODIO, Evan ,  BALLE, Susanne M. ,  BERNAT, Francesc Guim ,  PUTYRSKI, Slawomir ,  GRECCO, Joe ,  MITCHEL, Henry

IPC分类号： G06F15/78 ,  G06F9/54 ,  G06F9/50

摘要： Technologies for providing efficient reprovisioning in an accelerator device include an accelerator sled. The accelerator sled includes a memory and an accelerator device coupled to the memory. The accelerator device is to configure itself with a first bit stream to establish a first kernel, execute the first kernel to produce output data, write the output data to the memory, configure itself with a second bit stream to establish a second kernel, and execute the second kernel with the output data in the memory used as input data to the second kernel. Other embodiments are also described and claimed.

公开(公告)号：EP3382548A1

公开(公告)日：2018-10-03

申请号：EP18154434.7

申请日：2018-01-31

申请人： Intel Corporation

发明人： BERNAT, Francesc Guim ,  BARRAGAN, Daniel Rivas ,  DOSHI, Kshitij A. ,  SCHMISSEUR, Mark A.

IPC分类号： G06F9/54 ,  H04L29/12 ,  H04L12/46 ,  G06F12/0817

CPC分类号： G06F13/1663 ,  G06F9/544 ,  G06F9/545 ,  G06F12/082 ,  G06F12/0822 ,  G06F12/0831 ,  G06F12/1018 ,  G06F2212/1024 ,  G06F2212/621 ,  H04L12/4625 ,  H04L49/9068

摘要： In an example, there is disclosed a host-fabric interface (HFI), including: an interconnect interface to communicatively couple the HFI to an interconnect; a network interface to communicatively couple the HFI to a network; network interface logic to provide communication between the interconnect and the network; a coprocessor configured to provide an offloaded function for the network; a memory; and a caching agent configured to: designate a region of the memory as a shared memory between the HFI and a core communicatively coupled to the HFI via the interconnect; receive a memory operation directed to the shared memory; and issue a memory instruction to the memory according to the memory operation.

公开(公告)号：EP3995967A1

公开(公告)日：2022-05-11

申请号：EP21198635.1

申请日：2021-09-23

申请人： Intel Corporation

发明人： BERNAT, Francesc Guim ,  KUMAR, Karthik ,  BACHMUTSKY, Alexander ,  LU, Zhongyan ,  WILLHALM, Thomas

IPC分类号： G06F12/02 ,  G06F12/0868 ,  G06F12/0888 ,  G06F12/127 ,  G06F12/128 ,  H04L67/568 ,  H04L67/566 ,  H04L45/74 ,  G06F12/1036 ,  G06F12/0811 ,  G06F12/0831

摘要： Methods and apparatus for software-defined coherent caching of pooled memory. The pooled memory is implemented in an environment having a disaggregated architecture where compute resources such as compute platforms are connected to disaggregated memory via a network or fabric. Software-defined caching policies are implemented in hardware in a processor SoC or discrete device such as a Network Interface Controller (NIC) by programming logic in an FPGA or accelerator on the SoC or discrete device. The programmed logic is configured to implement software-defined caching policies in hardware for effecting disaggregated memory (DM) caching in an associated DM cache of at least a portion of an address space allocated for the software application in the disaggregated memory. In connection with DM cache operations, such as cache lines evicted from a CPU, logic implemented in hardware determines whether a cache line in a DM cache is to be convicted and implements the software-defined caching policy for the DM cache including associated memory coherency operations.

公开(公告)号：EP3731101A1

公开(公告)日：2020-10-28

申请号：EP20164272.5

申请日：2020-03-19

申请人： INTEL Corporation

发明人： BERNAT, Francesc Guim ,  ZIAKAS, Dimitrios ,  SCHMISSEUR, Mark ,  DOSHI, Kshitij ,  MALONE, Kimberly

IPC分类号： G06F12/06 ,  G06F12/1036 ,  G06F12/02 ,  G06N3/063 ,  G06F9/50 ,  G06N3/04 ,  G06F13/16

摘要： A semiconductor chip is described. The semiconductor chip includes memory address decoder logic circuitry comprising different memory address bit manipulation paths to respectively impose different memory interleaving schemes for memory accesses directed to artificial intelligence information in a memory and non artificial intelligence information in the memory. The artificial intelligence information is to be processed with artificial intelligence logic circuitry disposed locally to the memory.

公开(公告)号：EP3716107A1

公开(公告)日：2020-09-30

申请号：EP20158073.5

申请日：2020-02-18

申请人： Intel Corporation

发明人： VERRALL, Timothy ,  SOOD, Kapil ,  SMITH, Ned M. ,  VISWANATHAN, Tarun ,  DOSHI, Kshitij Arun ,  VUL, Alexander ,  BERNAT, Francesc Guim ,  MANISH, Dave

IPC分类号： G06F21/44 ,  H04L29/08 ,  G06F21/57 ,  H04L12/24 ,  H04L29/06

摘要： Technologies for accelerated orchestration and attestation include multiple edge devices. An edge appliance device performs an attestation process with each of its components to generate component certificates. The edge appliance device generates an appliance certificate that is indicative of the component certificates and a current utilization of the edge appliance device and provides the appliance certificate to a relying party. The relying party may be an edge orchestrator device. The edge orchestrator device receives a workload scheduling request with a service level agreement requirement. The edge orchestrator device verifies the appliance certificate and determines whether the service level agreement requirement is satisfied based on the appliance certificate. If satisfied, the workload is scheduled to the edge appliance device. Attestation and generation of the appliance certificate by the edge appliance device may be performed by an accelerator of the edge appliance device. Other embodiments are described and claimed.

公开(公告)号：EP3739448A1

公开(公告)日：2020-11-18

申请号：EP20161763.6

申请日：2020-03-09

申请人： INTEL Corporation

发明人： BALLE, Susanne M. ,  CUSTODIO, Evan ,  BERNAT, Francesc Guim

IPC分类号： G06F9/445 ,  G06F9/50

摘要： Technologies for compressing communications for accelerator devices are disclosed. An accelerator device may include a communication abstraction logic units to manage communication with one or more remote accelerator devices. The communication abstraction logic unit may receive communication to and from a kernel on the accelerator device. The communication abstraction logic unit may compress and decompress the communication without instruction from the corresponding kernel. The communication abstraction logic unit may choose when and how to compress communications based on telemetry of the accelerator device and the remote accelerator device.