公开(公告)号：EP4495761A1

公开(公告)日：2025-01-22

申请号：EP23220407.3

申请日：2023-12-27

Applicant: INTEL Corporation

Inventor： Agron, Jason ,  Kleen, Andreas ,  Chou, Ching-Tsun ,  Combs, Jonathan ,  Lu, Hongjiu ,  Stark IV, Jared Warner ,  Wiedemeier, Jeff

IPC: G06F9/30 ,  G06F9/32

Abstract: Techniques for performing an unconditional jump are described. In some examples, an instruction is processed to perform the unconditional jump. In some examples, the instruction is to at least include one or more fields for an opcode and a 64-bit bit immediate, wherein the 64-bit immediate is to encode an absolute address and the opcode is to indicate execution circuitry is jump to the absolute address.

公开(公告)号：EP4300294A1

公开(公告)日：2024-01-03

申请号：EP23173511.9

申请日：2023-05-16

Applicant: Intel Corporation

Inventor： Adelman, Menachem ,  Gradstein, Amit ,  Shemy, Regev ,  Natarajan, Chitra ,  Borges, Leonardo ,  Shivaswamy, Chytra ,  Ermolaev, Igor ,  Espig, Michael ,  Beit Aharon, Or ,  Wiedemeier, Jeff

IPC: G06F9/30

Abstract: Techniques for performing horizontal reductions are described. In some examples, an instance of a horizontal instruction is to include at least one field for an opcode, one or more fields to reference a first source operand, and one or more fields to reference a destination operand, wherein the opcode is to indicate that execution circuitry is, in response to a decoded instance of the single instruction, to at least perform a horizontal reduction using at least one data element of a non-masked data element position of at least the first source operand and store a result of the horizontal reduction in the destination operand.