公开(公告)号：EP4435614A1

公开(公告)日：2024-09-25

申请号：EP23217049.8

申请日：2023-12-15

申请人： INTEL Corporation

发明人： Lawlor, Jay ,  Sheffield, David ,  Zou, Xiang ,  Kinney, Michael ,  Holthaus, Charles ,  Toll, Thomas ,  Yitbarek, Salessawi Ferede ,  Kleen, Andreas ,  Tiruvallur, Keshavan ,  Jayakumar, Sarathy ,  Ni, Ruiyu

IPC分类号： G06F12/14 ,  G06F12/1009 ,  G06F9/4401

CPC分类号： G06F12/1009 ,  G06F2212/100420130101 ,  G06F2212/102820130101 ,  G06F12/1441 ,  G06F12/1491 ,  G06F9/4403 ,  G06F9/4405 ,  G06F2212/105620130101

摘要： An apparatus and method for a more efficient system management mode. For example, one embodiment of a processor comprises: a plurality of cores, at least a first core of the plurality of cores to perform operations to cause the plurality of cores to enter into a system management mode (SMM), the operations comprising: allocating a memory region for a system management RAM (SMRAM); writing an SMRAM state save location to a first register; and generating a page table in the SMRAM, including mapping a virtual address space a physical address space.

公开(公告)号：EP4435593A1

公开(公告)日：2024-09-25

申请号：EP23212854.6

申请日：2023-11-29

申请人： Intel Corporation

发明人： Kleen, Andreas ,  Sheffield, David ,  Zou, Xiang ,  Brandt, Jason

IPC分类号： G06F9/4401 ,  G06F21/57

CPC分类号： G06F9/441 ,  G06F9/4401

摘要： An apparatus and method for booting a processor directly into a paged 64-bit execution environment. For example, one embodiment of an a processor comprises: a register to store a first value and a second value related to a secure boot process; a plurality of cores, at least one of which performs operations comprising: receiving a first initialization message, the core to clear a plurality of registers responsively; receiving a second initialization message and reading the first and second values responsively, the first value indicating whether a first initialization mode is supported, and the second value comprising an address pointer identifying a data structure comprising a plurality of state values; and initializing a paged 64-bit execution environment using the state values from the data structure responsive to the first value indicating the first initialization mode is supported and the data structure indicating enabling the paged 64-bit execution environment.

公开(公告)号：EP4432104A1

公开(公告)日：2024-09-18

申请号：EP23214261.2

申请日：2023-12-05

申请人： INTEL Corporation

发明人： Brandt, Jason ,  Ouziel, Ido ,  Chynoweth, Michael ,  Rivas Toledano, Raoul ,  Neiger, Gilbert ,  Kleen, Andreas ,  Doweck, Jacob ,  Nelson, Andrew

IPC分类号： G06F12/1027

CPC分类号： G06F12/1027 ,  G06F2212/68220130101 ,  G06F2212/68320130101

摘要： An apparatus and method are described for reduced power TLB management. For example, one embodiment of a processor comprises: a plurality of cores; a first core of the plurality of cores comprising: a first translation lookaside buffer (TLB) to store address translations associated with page table walk operations, and power management logic to cause the first core to enter into a first low power state in which the address translations in the first TLB are no longer valid, wherein prior to entering into the low power state, the first core is to write an indication in a memory location that the first TLB no longer contains valid address translations; a second core of the plurality of cores to perform an operation requiring invalidation of one or more of the address translations previously stored in the first TLB, the second core to determine whether to transmit a request to the first core to invalidate the one or more address translations based on the indication.

公开(公告)号：EP4254197A1

公开(公告)日：2023-10-04

申请号：EP23156438.6

申请日：2023-02-14

申请人： INTEL Corporation

发明人： Merten, Matthew ,  Strong, Beeman ,  Cohen, Moshe ,  Yasin, Ahmad ,  Kleen, Andreas ,  Bratanov, Stanislav ,  Gopalakrishnan, Karthik ,  Schmid, Angela ,  Zhou, Grant

IPC分类号： G06F11/30 ,  G06F11/34 ,  G06F11/36

摘要： Techniques and mechanisms for configuring processor event-based sampling (PEBS) with a set of control registers. In an embodiment, a first control register of a processor is programmed to store a physical address of a location in a buffer which receives PEBS records. The first control register is further programmed or otherwise configured to store an indication of a size of the buffer. A second control register of the processor stores a physical address of a location in the buffer were a next PEBS record is to be stored. In another embodiment, the processor further comprises multiple control registers which variously configure PEBS generation on a per-counter basis.