公开(公告)号：EP0696052A2

公开(公告)日：1996-02-07

申请号：EP95480080.1

申请日：1995-06-22

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Chen, Bomy Able ,  Nguyen, Son van ,  Bronner, Gary Bela

IPC分类号： H01L21/3205 ,  H01L21/033 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/40 ,  Y10S438/947

摘要： Integrated circuit structures of sub-lithography dimensions are formed by conformal deposition of alternating layers of materials having differing etch rates within an aperture over a body of material to be etched. One of the materials in the alternating layers is then selectively and preferentially etched to form a mask through which etching can be performed on the body of material to be etched. Large polysilicon blocks or plugs (38) are formed onto a conventional interconnect structure for accessing a memory cell prior to forming a capacitor which can extend over a portion of a bit line and the insulating cap and sidewalls. This is preferably done by providing a thick polysilicon deposition in a blanket layer by any known process. This blanket layer is then preferably planarized and then etched to separate the layer into blocks or plugs which are in contact with the conductive studs connected to transistors. Deep grooves are formed in the polysilicon plug (38). The polysilicon plug is surrounded with TEOS oxide and includes concentric rings which are of sustantial mechanical integrity, particularly after a oxide-nitride-oxide (ONO) layer (60) of about 5 nm thickness is conformally deposited in the grooves and the remainder of the grooves are filled with a conductor (62) such as aluminium or polysilicon to complete the other capacitor plate. This technique is particularly suited to the formation of structurally robust capacitors for memory cells which have greatly increased plate area, resulting in increased capacitance, while maintaining a small footprint for the capacitor structure.

摘要翻译： 亚光刻尺寸的集成电路结构通过在待蚀刻材料体上的孔内的不同蚀刻速率的交替层材料的共形沉积形成。 然后选择性地和优先地蚀刻交替层中的一种材料以形成掩模，通过该掩模可以对要蚀刻的材料的主体进行蚀刻。 在形成电容器之前，将大多晶硅块或插头（38）形成在常规的互连结构上，用于访问存储器单元，该电容器可以在位线的一部分和绝缘盖和侧壁上延伸。 优选通过任何已知方法在覆盖层中提供厚的多晶硅沉积来完成。 然后优选将该覆盖层平面化，然后蚀刻以将该层分离成与连接到晶体管的导电柱相接触的块或插塞。 在多晶硅塞（38）中形成有深沟槽。 多晶硅插塞被TEOS氧化物包围，并且包括具有维持机械完整性的同心环，特别是在约5nm厚度的氧化物 - 氮化物 - 氧化物（ON））层（60）共形沉积在凹槽中并且其余部分 沟槽填充有诸如铝或多晶硅的导体（62），以完成另一个电容器板。 该技术特别适用于形成用于存储器单元的结构稳健的电容器，其大大增加了板面积，导致增加的电容，同时保持电容器结构的小的占地面积。 $$