公开(公告)号：EP0486167A3

公开(公告)日：1993-08-04

申请号：EP91309773.9

申请日：1991-10-22

申请人： International Business Machines Corporation

发明人： Desnoyers, Christine Marie ,  Garmire, Derrick Leroy ,  Genco, Sheryl Marie ,  Grice, Donald George ,  Milani, William Robert ,  Muhlada, Michael Patrick ,  Myers, Donna Carol ,  Szwed, Peter Kenneth ,  Tsinker, Vadim Miron ,  Vallone, Antoinette Elaine ,  Bender, Carl Alfred

IPC分类号： G06F15/16

CPC分类号： G06F15/17375 ,  F02B2075/027

摘要： A combiner/memory system interconnects a plurality of computer systems using for example the new HIPPI standard link. The combiner system includes it's own internal storage for rapid shared access to all connected computer systems. The combiner/memory system includes a smart switch for reading header information, arbitrating messages and connecting computers to each other or to the internal shared storage. The system also includes a mechanism for synchronization of cooperating processes.

摘要翻译： 组合器/存储器系统使用例如新的HIPPI标准链路来互连多个计算机系统。 组合器系统包括它自己的内部存储器，用于快速共享所有连接的计算机系统。 组合器/存储器系统包括用于读取标题信息，仲裁消息以及将计算机彼此连接或连接到内部共享存储器的智能开关。 该系统还包括用于协作过程同步的机制。

公开(公告)号：EP0486167A2

公开(公告)日：1992-05-20

申请号：EP91309773.9

申请日：1991-10-22

申请人： International Business Machines Corporation

发明人： Desnoyers, Christine Marie ,  Garmire, Derrick Leroy ,  Genco, Sheryl Marie ,  Grice, Donald George ,  Milani, William Robert ,  Muhlada, Michael Patrick ,  Myers, Donna Carol ,  Szwed, Peter Kenneth ,  Tsinker, Vadim Miron ,  Vallone, Antoinette Elaine ,  Bender, Carl Alfred

IPC分类号： G06F15/16

CPC分类号： G06F15/17375 ,  F02B2075/027

摘要： A combiner/memory system interconnects a plurality of computer systems using for example the new HIPPI standard link. The combiner system includes it's own internal storage for rapid shared access to all connected computer systems. The combiner/memory system includes a smart switch for reading header information, arbitrating messages and connecting computers to each other or to the internal shared storage. The system also includes a mechanism for synchronization of cooperating processes.

摘要翻译： 组合器/存储器系统使用例如新的HIPPI标准链路来互连多个计算机系统。 组合器系统包括它自己的内部存储器，用于快速共享所有连接的计算机系统。 组合器/存储器系统包括用于读取标题信息，仲裁消息以及将计算机彼此连接或连接到内部共享存储器的智能开关。 该系统还包括用于协作过程同步的机制。

公开(公告)号：EP0687986A3

公开(公告)日：1996-02-14

申请号：EP95107081.2

申请日：1995-05-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Garmire, Derrick Leroy ,  Capowski, Robert Stanley ,  Casper, Daniel Francis ,  Desnoyers, Christine Marie ,  Ferraiolo, Frank David ,  Halma, Marten Jan ,  Stucke, Robert Frederick

IPC分类号： G06F15/17 ,  G06F13/12 ,  G06F15/16

CPC分类号： G06F15/17375 ,  G06F13/4256 ,  G06F15/17

摘要： A massively parallel system has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. Digital data is transmitted at high speeds via the parallel bus to provide a scalable communications network for parallel processing systems while eliminating precise bus length and system clock rates as a critical or limiting factor.

公开(公告)号：EP0687986A2

公开(公告)日：1995-12-20

申请号：EP95107081.2

申请日：1995-05-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Garmire, Derrick Leroy ,  Capowski, Robert Stanley ,  Casper, Daniel Francis ,  Desnoyers, Christine Marie ,  Ferraiolo, Frank David ,  Halma, Marten Jan ,  Stucke, Robert Frederick

IPC分类号： G06F15/17 ,  G06F13/12 ,  G06F15/16

CPC分类号： G06F15/17375 ,  G06F13/4256 ,  G06F15/17

摘要： A massively parallel system has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. Digital data is transmitted at high speeds via the parallel bus to provide a scalable communications network for parallel processing systems while eliminating precise bus length and system clock rates as a critical or limiting factor.

摘要翻译： 大规模并行系统具有自定义接口（STI），其中时钟信号将位串行数据时钟并入并行导电总线，并且时钟信号在总线的单独线路上传输。 总线上每条线上的接收数据与时钟信号单独相位对准。 数字数据通过并行总线以高速传输，为并行处理系统提供可扩展的通信网络，同时消除了精确的总线长度和系统时钟速率作为关键或限制因素。 $$