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    A technique for accomplishing deadlock free routing through a multi-stage cross-point packet switch
    2.
    发明公开
    A technique for accomplishing deadlock free routing through a multi-stage cross-point packet switch 失效
    Eine Technik zum Erreichen eines blockierungsfreien Durchschaltens eines Mehrstufen-Koppelpunkt-Packetschalters。

    公开(公告)号：EP0676703A2

    公开(公告)日：1995-10-11

    申请号：EP95100957.0

    申请日：1995-01-25

    申请人： International Business Machines Corporation

    发明人： Sethu, Harish ,  Stucke, Robert Frederick ,  Stunkel, Craig Brian

    IPC分类号： G06F15/16 ,  G06F15/173

    CPC分类号： H04L45/00

    摘要： Apparatus and an accompanying method for establishing deadlock-free routing in a large bi-directional multi-stage inter-connected cross-point based packet switch, particularly, though not exclusively, that employed within a high speed packet network of a massively parallel processing system (400). Specifically, in selecting routes for inclusion within route tables (320, 360, 380) contained within the system, the entire network is effectively partitioned such that certain routes would be prohibited in order to isolate packet traffic that would flow solely between nodes in one partition, e.g. system half (503), of the system from packet traffic that would flow between nodes in the other partition, e.g. another system half (507). In that regard, to pick routes for packets that are to transit between nodes situated in a common partition of the system, those routes that contain a path(s) (524, 544) passing through the other system partition would be prohibited. No such route prohibition would occur in selecting a route that is to carry a packet between nodes in multiple system partitions, e.g. between different halves of the system.

    摘要翻译： 通过多级交叉点分组交换机的无死锁自由路由的技术涉及通过网络定义若干规定的路由，使得可以通过不同对应点从节点内的各个节点承载分组。 路由到节点内的每个其他节点。 每个定义的路由至少延伸一个链路。 定义的路由被定义为将网络解析成分别连接到两组不同节点的两个分区，使得将在第一组中的两个节点之间传输并且仅连接到第一网络分区的分组将不被转移 具有延伸到第二网络分区中的链路的任何路由。 所有规定的路线都存储在生成的路由表中。

    Multiprocessor system
    4.
    发明公开
    Multiprocessor system 失效
    Multiprozessorsystem。

    公开(公告)号：EP0543512A2

    公开(公告)日：1993-05-26

    申请号：EP92309804.0

    申请日：1992-10-27

    申请人： International Business Machines Corporation

    发明人： Coleman, John Joseph ,  Coleman, Ronald Gerald ,  Monroe, Owen Keith ,  Stucke, Robert Frederick ,  Vanderbeck, Elizabeth Anne ,  Bello, Stephen Edward ,  Hattersley, John Robert ,  Hua, Kien Anh ,  Pruett, David Raymond ,  Rollo, Gerald Franklin

    IPC分类号： G06F15/16

    CPC分类号： G06F15/17375

    摘要： A parallel computer system is disclosed comprising a plurality of high level processors joined together using a cross-point or cross-bar switch. The system includes an adapter between each processor and the switch. Protocol processing to drive the switch, transfer pages and schedule transmissions between the processor is performed by the adapter. The protocol use the notion of typed or tagged buffer management that allows a client to bind the semantics of a message being sent or received. These semantics specify behaviours in the protocol when message packets depart or when they arrive.

    摘要翻译： 公开了一种并行计算机系统，其包括使用交叉点或横杆开关连接在一起的多个高级处理器。 该系统包括每个处理器和交换机之间的适配器。 用于驱动交换机的协议处理，在处理器之间传送页面和调度传输由适配器执行。 该协议使用类型化或标记的缓冲区管理的概念，允许客户端绑定正在发送或接收的消息的语义。 这些语义在消息包离开或到达时指定协议中的行为。

    Multiprocessor system
    7.
    发明公开
    Multiprocessor system 失效
    多处理器系统

    公开(公告)号：EP0543512A3

    公开(公告)日：1995-02-01

    申请号：EP92309804.0

    申请日：1992-10-27

    申请人： International Business Machines Corporation

    发明人： Coleman, John Joseph ,  Coleman, Ronald Gerald ,  Monroe, Owen Keith ,  Stucke, Robert Frederick ,  Vanderbeck, Elizabeth Anne ,  Bello, Stephen Edward ,  Hattersley, John Robert ,  Hua, Kien Anh ,  Pruett, David Raymond ,  Rollo, Gerald Franklin

    IPC分类号： G06F15/16

    CPC分类号： G06F15/17375

    摘要： A parallel computer system is disclosed comprising a plurality of high level processors joined together using a cross-point or cross-bar switch. The system includes an adapter between each processor and the switch. Protocol processing to drive the switch, transfer pages and schedule transmissions between the processor is performed by the adapter. The protocol use the notion of typed or tagged buffer management that allows a client to bind the semantics of a message being sent or received. These semantics specify behaviours in the protocol when message packets depart or when they arrive.

    摘要翻译： 公开了一种并行计算机系统，包括使用交叉点或交叉开关连接在一起的多个高级处理器。 该系统在每个处理器和交换机之间包含一个适配器。 通过适配器执行协议处理以驱动交换机，传输页面和调度处理器之间的传输。 该协议使用类型化或标记缓冲区管理的概念，允许客户端绑定正在发送或接收的消息的语义。 这些语义在消息分组离开或到达时指定协议中的行为。

    A technique for accomplishing deadlock free routing through a multi-stage cross-point packet switch
    9.
    发明公开
    A technique for accomplishing deadlock free routing through a multi-stage cross-point packet switch 失效
    用于实现非阻塞通过多级交叉点分组交换机的切换的技术。

    公开(公告)号：EP0676703A3

    公开(公告)日：1996-02-07

    申请号：EP95100957.0

    申请日：1995-01-25

    申请人： International Business Machines Corporation

    发明人： Sethu, Harish ,  Stucke, Robert Frederick ,  Stunkel, Craig Brian

    IPC分类号： G06F15/16 ,  G06F15/173

    CPC分类号： H04L45/00

    摘要： Apparatus and an accompanying method for establishing deadlock-free routing in a large bi-directional multi-stage inter-connected cross-point based packet switch, particularly, though not exclusively, that employed within a high speed packet network of a massively parallel processing system (400). Specifically, in selecting routes for inclusion within route tables (320, 360, 380) contained within the system, the entire network is effectively partitioned such that certain routes would be prohibited in order to isolate packet traffic that would flow solely between nodes in one partition, e.g. system half (503), of the system from packet traffic that would flow between nodes in the other partition, e.g. another system half (507). In that regard, to pick routes for packets that are to transit between nodes situated in a common partition of the system, those routes that contain a path(s) (524, 544) passing through the other system partition would be prohibited. No such route prohibition would occur in selecting a route that is to carry a packet between nodes in multiple system partitions, e.g. between different halves of the system.

    Packaging system
    10.
    发明公开
    Packaging system 失效
    Verpackungsanordnung。

    公开(公告)号：EP0554077A1

    公开(公告)日：1993-08-04

    申请号：EP93300600.9

    申请日：1993-01-27

    申请人： International Business Machines Corporation

    发明人： Stucke, Robert Frederick

    IPC分类号： H05K7/10

    CPC分类号： H05K1/14 ,  H05K7/1445

    摘要： A high density interconnection system for connecting large numbers of unique signal lines between orthogonally positioned circuit cards, utilizes pins (12) from the back of a zero insertion force connector (ZIF) (14) to extend through the interconnection card (10) and mate with a female socket connector (20) on a second circuit board (24). Pins from the ZIF connector which are not aligned with the sockets of the orthogonally positioned socket connector may be connected to pins on the interconnection card which are aligned with the socket connector but not the ZIF. Very high numbers of connections between circuit cards may be made in a small volume and maintain signal line length at a minimum to ensure maximum signal transfer speed.

    摘要翻译： 用于在正交定位的电路卡之间连接大量唯一信号线的高密度互连系统利用来自零插入力连接器（ZIF）（14）的背面的引脚（12）延伸通过互连卡（10）并配合 在第二电路板（24）上具有母插座连接器（20）。 来自ZIF连接器的未与正交定位的插座连接器的插座对准的引脚可以连接到互连卡上与插座连接器对准而不是ZIF的引脚。 电路卡之间的连接数量可能很小，并且将信号线长度保持在最小，以确保最大的信号传输速度。