METHOD AND SYSTEM FOR PROCESSING FLOATING POINT NUMBERS

    公开(公告)号:EP3958113A1

    公开(公告)日:2022-02-23

    申请号:EP21190433.9

    申请日:2021-08-09

    发明人: Ferrere, Thomas

    IPC分类号: G06F7/485 G06F7/509

    摘要: A method and system for processing a set of 'k' floating point numbers to perform addition and/or subtraction is disclosed. Each floating-point number comprises a mantissa (m i ) and an exponent (e i ). The method comprises receiving the set of 'k' floating point numbers in a first format, each floating-point number in the first format comprising a mantissa (m i ) with a bit-length of 'b' bits. The method further comprises creating a set of 'k' numbers (y i ) based on the mantissas of the 'k' floating-point numbers, the numbers having a bit-length of 'n' bits obtained by adding both extra most-significant bits and extra least-significant bits to the bit length 'b' of the mantissa (m i ). The method includes identifying a maximum exponent (e max ) among the exponents e i , aligning the magnitude bits of the numbers (y i ) based on the maximum exponent (e max ) and processing the set of 'k' numbers concurrently.

    METHOD AND SYSTEM FOR CALCULATING DOT PRODUCTS

    公开(公告)号:EP4231135A1

    公开(公告)日:2023-08-23

    申请号:EP23155922.0

    申请日:2023-02-09

    发明人: Ferrere, Thomas

    IPC分类号: G06F7/483 G06F7/544

    摘要: A method of performing dot product of an array of '2k' floating point numbers comprising two sets of k floating-point numbers a i and b i is disclosed. The method includes receiving both sets of 'k' floating point numbers and multiplying each floating point number a i with a floating point number b i to generate k product numbers (z i ), each product number (z i ) having a mantissa bit length of 'r' bits. The method further comprises creating a set of 'k' numbers (y i ) based on the k product numbers (z i ), the numbers (y i ) having a bit-length of 'n' bits. Further the method includes identifying a maximum exponent sum (e max ) among k exponent sums (eab i ) of each pair of floating point numbers a i and b i , aligning the magnitude bits of the numbers (y i ) based on the maximum exponent sum (e max ) and adding the set of 'k' numbers concurrently to obtain the dot product.

    METHOD AND SYSTEM FOR CALCULATING DOT PRODUCTS

    公开(公告)号:EP4231134A1

    公开(公告)日:2023-08-23

    申请号:EP23155921.2

    申请日:2023-02-09

    发明人: Ferrere, Thomas

    IPC分类号: G06F7/483 G06F7/544

    摘要: A method of performing dot product of an array of '2k' floating point numbers comprising two sets of k floating-point numbers a i and b i is disclosed. The method includes receiving both sets of 'k' floating point numbers and multiplying each floating point number a i with a floating point number b i to generate k product numbers (z i ), each product number (z i ) having a mantissa bit length of 'r+ log (k-1) +1' bits. The method further comprises creating a set of 'k' numbers (y i ) based on the k product numbers (z i ), the numbers (y i ) having a bit-length of 'n' bits. Further the method includes identifying a maximum exponent sum (e max ) among k exponent sums (eab i ) of each pair of floating point numbers a i and b i , aligning the magnitude bits of the numbers (y i ) based on the maximum exponent sum (e max ) and adding the set of 'k' numbers concurrently to obtain the dot product.

    METHOD AND SYSTEM FOR VERIFYING A SORTER
    4.
    发明公开

    公开(公告)号:EP3882761A1

    公开(公告)日:2021-09-22

    申请号:EP21161631.3

    申请日:2021-03-09

    IPC分类号: G06F7/24 G06F30/3323

    摘要: Methods and systems of verifying a hardware design for a sorter are disclosed. The methods include generating a modified version of the hardware design of the sorter accepting extended inputs and performing formal verification comprising: implementing a constraint that the least significant bits of each input in a set of extended inputs represent a unique value; and formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.