VERFAHREN UND SYSTEM ZUR DIGITALEN ECHTZEIT-DATENVERARBEITUNG
    1.
    发明公开
    VERFAHREN UND SYSTEM ZUR DIGITALEN ECHTZEIT-DATENVERARBEITUNG 有权
    方法和系统数字实时数据处理

    公开(公告)号:EP1364299A1

    公开(公告)日:2003-11-26

    申请号:EP02719931.4

    申请日:2002-02-26

    IPC分类号: G06F15/78 G06F9/46 G06F13/40

    CPC分类号: H04J3/047

    摘要: The invention relates to a digital real-time data processing system that processes digital input data streams, which are received by several digital data sources (4), into digital output data streams and transfers them to digital data sinks (32). The digital data processing system (1) comprises a control unit (20) for controlling a multiplexer (13), a demultiplexer (25) and a digital data processing unit (17), whereby the control unit (20) cyclically interconnects the inputs (12) of the multiplexer for a constant fraction of time (Ti) of the cycle time (Tcycle) to a data input (16) of the data processing unit (17), whereby the control unit cyclically interconnects the outputs (29) of the demultiplexer (25) for a constant fraction of time (Ti) to the associated digital data sinks (32), and the control unit (20) activates the data processing unit (17) for processing the data, which is connected through by the multiplexer (13) and which is of a digital input data stream received with a defined data transmission rate, for a variable data processing time (Tactive).

    IMPROVED ARCHITECTURE WITH SHARED MEMORY
    4.
    发明公开
    IMPROVED ARCHITECTURE WITH SHARED MEMORY 审中-公开
    改进的架构共享存储器

    公开(公告)号:EP1490764A2

    公开(公告)日:2004-12-29

    申请号:EP03745789.2

    申请日:2003-04-04

    IPC分类号: G06F9/46 G06F12/06

    CPC分类号: G06F13/1652 G06F12/0607

    摘要: A system with multiple processors sharing a single memory module without noticeable performance degradation is described. The memory module is divided into n independently addressable banks, where n is at least 2 and mapped such that sequential addresses are rotated between the banks. Such a mapping causes sequential data bytes to be stored in alternate banks. Each bank may be further divided into a plurality of blocks. By staggering or synchronizing the processors to execute the computer program such that each processor access a different block during the same cycle, the processorts can access the memory simltaneously. Additionally, a cache is provided to enable a processor to fetch from memory a plurality of data words from different memory banks to reduce memory latency caused by memory contention.

    VERFAHREN UND SYSTEM ZUR DIGITALEN ECHTZEIT-DATENVERARBEITUNG
    9.
    发明授权
    VERFAHREN UND SYSTEM ZUR DIGITALEN ECHTZEIT-DATENVERARBEITUNG 有权
    方法和系统数字实时数据处理

    公开(公告)号:EP1364299B1

    公开(公告)日:2006-05-17

    申请号:EP02719931.4

    申请日:2002-02-26

    IPC分类号: G06F15/78 G06F9/46 G06F13/40

    CPC分类号: H04J3/047

    摘要: The invention relates to a digital real-time data processing system that processes digital input data streams, which are received by several digital data sources (4), into digital output data streams and transfers them to digital data sinks (32). The digital data processing system (1) comprises a control unit (20) for controlling a multiplexer (13), a demultiplexer (25) and a digital data processing unit (17), whereby the control unit (20) cyclically interconnects the inputs (12) of the multiplexer for a constant fraction of time (Ti) of the cycle time (Tcycle) to a data input (16) of the data processing unit (17), whereby the control unit cyclically interconnects the outputs (29) of the demultiplexer (25) for a constant fraction of time (Ti) to the associated digital data sinks (32), and the control unit (20) activates the data processing unit (17) for processing the data, which is connected through by the multiplexer (13) and which is of a digital input data stream received with a defined data transmission rate, for a variable data processing time (Tactive).