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公开(公告)号：EP1017095A2
公开(公告)日：2000-07-05
申请号：EP99310310.0
申请日：1999-12-21
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10867 , H01L27/10876
摘要： A memory cell formed in a semiconductor body includes a vertical trench with a polysilicon fill as a storage capacitor and a field effect transistor having a source formed in the sidewall of the trench, a drain formed in the semiconductor body and having a surface common with a top surface of the semiconductor body, and having a channel region that includes both vertical and horizontal portions and a polysilicon gate that is in an upper portion of the trench. A process for fabrication provides an insulating oxide layer at the top of the polysilicon fill portion that serves as the storage node and the polysilicon fill portion that serves as the gate conductor.
摘要翻译： 形成在半导体本体中的存储单元包括具有作为存储电容器的多晶硅填充物的垂直沟槽和具有形成在沟槽的侧壁中的源极的场效应晶体管，形成在半导体本体中并且具有与 并且具有包括垂直部分和水平部分的沟道区域以及位于沟道上部的多晶硅栅极。 用于制造的工艺在用作存储节点的多晶硅填充部分的顶部和用作栅极导体的多晶硅填充部分处提供绝缘氧化物层。
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公开(公告)号：EP0847010B1
公开(公告)日：2003-01-22
申请号：EP97309474.1
申请日：1997-11-25
发明人： DeBrosse, John , Kirihata, Toshiaki , Wong, Hing
IPC分类号： G06F11/20
CPC分类号： G11C29/80 , G11C29/808 , G11C29/84
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公开(公告)号：EP0847010A2
公开(公告)日：1998-06-10
申请号：EP97309474.1
申请日：1997-11-25
发明人： DeBrosse, John , Kirihata, Toshiaki , Wong, Hing
IPC分类号： G06F11/20
CPC分类号： G11C29/80 , G11C29/808 , G11C29/84
摘要： Row redundancy control circuits which effectively reduce design space are arranged parallel to word direction and are arranged at the bottom of the redundancy block. This architecture change makes it possible to effectively lay out the redundancy control block by introducing (1) split-global-bus shared with local row redundancy wires, (2) half-length-one-way row redundancy-wordline-enable-signal wires which allows space saving, and (3) distributed wordline enable decoders designed to take advantage of the saved space. An illegal normal/redundancy access problem caused by the address versus timing skew has also been solved. The timing necessary for this detection is given locally by using its adjacent redundancy match detection. This allows the circuit to operate completely as an address driven circuit, resulting in fast and reliable redundancy match detection. In addition, a sample wordline enable signal (SWLE) is generated by using row redundancy match detection. One two-input OR gate allows the time at which SWLE sets sample wordline (SWL) to be the same as the time at which wordline enable (WLE) signal sets wordline (WL). The time at which SWLE sets SWL remains consistent regardless of mode, eliminating the existing reliability concern. This two-input OR gate combined with row redundancy match detection works as an ideal sample wordline enable generator.
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公开(公告)号：EP0889528B1
公开(公告)日：2010-08-18
申请号：EP98305124.4
申请日：1998-06-29
IPC分类号： H01L27/108 , G11C11/4097
CPC分类号： H01L27/10805 , H01L27/10882 , Y10S257/905 , Y10S257/907
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公开(公告)号：EP0889528A2
公开(公告)日：1999-01-07
申请号：EP98305124.4
申请日：1998-06-29
IPC分类号： H01L27/108
CPC分类号： H01L27/10805 , H01L27/10882 , Y10S257/905 , Y10S257/907
摘要： A dynamic random access memory array having an array of memory cells. Individual cells of the array are addressable by a plurality of word lines and a plurality of bit lines. The memory cells are disposed in active areas of the array. The array of memory cells includes a first strip of memory cells. The dynamic random access memory array includes a lower metal layer and an upper metal layer disposed above the lower metal layer. The dynamic random access memory array further includes a dielectric layer disposed between the lower metal layer and the upper metal layer. There is further included a first bit line of the plurality of bit lines which includes a lower metal first bit line portion implemented in the lower metal layer. The lower metal first bit line portion is coupled to a first plurality of memory cells of the first strip of memory cells. The first bit line also includes an upper metal first bit line portion implemented in the upper metal layer. The upper metal first bit line portion is coupled to the lower first metal bit line portion by a first contact through the dielectric layer. The first contact is disposed above one of the active areas.
摘要翻译： 该阵列由设置在有源区域（522）中的存储单元形成，每个存储单元可由一组相应的字线和位线寻址。 字线以预定角度倾斜到位线。 阵列中的第一条存储单元包括通过电介质层形成在下金属层上的上金属层。 在下金属层中形成位线（BL1），并连接到形成第一条带的存储单元。 在上金属层（bBL1）中形成位线，并通过设置在电介质层中的有源区（522）上方的触点（528）与下金属位线连接。
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公开(公告)号：EP1017095A3
公开(公告)日：2005-04-13
申请号：EP99310310.0
申请日：1999-12-21
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10867 , H01L27/10876
摘要： A memory cell formed in a semiconductor body includes a vertical trench (14) with a polysilicon fill (22) as a storage capacitor and a field effect transistor having a source (43) formed in the sidewall of the trench, a drain (42) formed in the semiconductor body (10) and having a surface common with a top surface of the semiconductor body, and having a channel region that includes both vertical and horizontal portions and a polysilicon gate (30) that is in an upper portion of the trench. A process for fabrication provides an insulating oxide layer (24A) at the top of the polysilicon fill portion (22) that serves as the storage node and a dielectric layer (28) that was formed as part of the gate dielectric of the transistor.
摘要翻译： 形成在半导体本体中的存储单元包括具有作为存储电容器的多晶硅填充物（22）的垂直沟槽（14）和形成在沟槽的侧壁中的源极（43）的场效应晶体管，漏极（42） 形成在所述半导体本体（10）中并且具有与所述半导体主体的顶表面共同的表面，并且具有包括垂直和水平部分的沟道区域和位于所述沟槽的上部的多晶硅栅极（30） 。 一种制造工艺在多晶硅填充部分（22）的顶部提供用作存储节点的绝缘氧化物层（24A）和形成为晶体管的栅极电介质的一部分的电介质层（28）。
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公开(公告)号：EP0889528A3
公开(公告)日：2002-01-16
申请号：EP98305124.4
申请日：1998-06-29
IPC分类号： H01L27/108 , G11C11/4097
CPC分类号： H01L27/10805 , H01L27/10882 , Y10S257/905 , Y10S257/907
摘要： A dynamic random access memory array having an array of memory cells. Individual cells of the array are addressable by a plurality of word lines and a plurality of bit lines. The memory cells are disposed in active areas of the array. The array of memory cells includes a first strip of memory cells. The dynamic random access memory array includes a lower metal layer and an upper metal layer disposed above the lower metal layer. The dynamic random access memory array further includes a dielectric layer disposed between the lower metal layer and the upper metal layer. There is further included a first bit line of the plurality of bit lines which includes a lower metal first bit line portion implemented in the lower metal layer. The lower metal first bit line portion is coupled to a first plurality of memory cells of the first strip of memory cells. The first bit line also includes an upper metal first bit line portion implemented in the upper metal layer. The upper metal first bit line portion is coupled to the lower first metal bit line portion by a first contact through the dielectric layer. The first contact is disposed above one of the active areas.
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公开(公告)号：EP0847010A3
公开(公告)日：1999-08-18
申请号：EP97309474.1
申请日：1997-11-25
发明人： DeBrosse, John , Kirihata, Toshiaki , Wong, Hing
IPC分类号： G06F11/20
CPC分类号： G11C29/80 , G11C29/808 , G11C29/84
摘要： Row redundancy control circuits which effectively reduce design space are arranged parallel to word direction and are arranged at the bottom of the redundancy block. This architecture change makes it possible to effectively lay out the redundancy control block by introducing (1) split-global-bus shared with local row redundancy wires, (2) half-length-one-way row redundancy-wordline-enable-signal wires which allows space saving, and (3) distributed wordline enable decoders designed to take advantage of the saved space. An illegal normal/redundancy access problem caused by the address versus timing skew has also been solved. The timing necessary for this detection is given locally by using its adjacent redundancy match detection. This allows the circuit to operate completely as an address driven circuit, resulting in fast and reliable redundancy match detection. In addition, a sample wordline enable signal (SWLE) is generated by using row redundancy match detection. One two-input OR gate allows the time at which SWLE sets sample wordline (SWL) to be the same as the time at which wordline enable (WLE) signal sets wordline (WL). The time at which SWLE sets SWL remains consistent regardless of mode, eliminating the existing reliability concern. This two-input OR gate combined with row redundancy match detection works as an ideal sample wordline enable generator.
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