公开(公告)号：EP1039534A2

公开(公告)日：2000-09-27

申请号：EP00103845.4

申请日：2000-02-24

申请人： Infineon Technologies North America Corp. ,  International Business Machines Corporation

发明人： Gruening, Ulrike ,  Halle, Scott ,  Radens, Carl J. ,  Welser, Jeffrey J. ,  Beintner, Jochen ,  Mandelman, Jack A. ,  Wittmann, Juergen

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10864 ,  H01L27/10861

摘要： A method includes forming a trench capacitor in a semiconductor body. A recess is formed in the upper portion of the capacitor with such recess having sidewalls in the semiconductor body. A first material is deposited over the sidewalls and over a bottom of the recess. A second material is deposited over the first material. A mask is provided over the second material. The mask has: a masking region to cover one portion of said recess bottom; and a window over a portion of said recess sidewall and another portion of said recess bottom to expose underlying portions of the second material. Portions of the exposed underlying portions of the second material are selectively removing while leaving substantially un-etched exposed underlying portions of the first material. The exposed portions of the first material and underlying portions of the semiconductor body are selectively removed. An isolation region is formed in the removed portions of the semiconductor body. The mask is provided over the second material with a masking region covering one portion of said recess sidewall and one portion of said recess bottom and with a window disposed over an opposite portion of said recess sidewall and an opposite portion of said recess bottom to expose underlying portions of the second material. Etching is provided into the exposed underlying portions of the semiconductor body to form a shallow trench in the semiconductor body. An insulating material is formed in the shallow trench to form a shallow trench isolation region. With such method, greater mask misalignment tolerances are permissible.

公开(公告)号：EP1039534A3

公开(公告)日：2001-04-04

申请号：EP00103845.4

申请日：2000-02-24

申请人： Infineon Technologies North America Corp. ,  International Business Machines Corporation

发明人： Gruening, Ulrike ,  Halle, Scott ,  Radens, Carl J. ,  Welser, Jeffrey J. ,  Beintner, Jochen ,  Mandelman, Jack A. ,  Wittmann, Juergen

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10864 ,  H01L27/10861

摘要： A method includes forming a trench capacitor in a semiconductor body. A recess is formed in the upper portion of the capacitor with such recess having sidewalls in the semiconductor body. A first material is deposited over the sidewalls and over a bottom of the recess. A second material is deposited over the first material. A mask is provided over the second material. The mask has: a masking region to cover one portion of said recess bottom; and a window over a portion of said recess sidewall and another portion of said recess bottom to expose underlying portions of the second material. Portions of the exposed underlying portions of the second material are selectively removing while leaving substantially un-etched exposed underlying portions of the first material. The exposed portions of the first material and underlying portions of the semiconductor body are selectively removed. An isolation region is formed in the removed portions of the semiconductor body. The mask is provided over the second material with a masking region covering one portion of said recess sidewall and one portion of said recess bottom and with a window disposed over an opposite portion of said recess sidewall and an opposite portion of said recess bottom to expose underlying portions of the second material. Etching is provided into the exposed underlying portions of the semiconductor body to form a shallow trench in the semiconductor body. An insulating material is formed in the shallow trench to form a shallow trench isolation region. With such method, greater mask misalignment tolerances are permissible.

摘要翻译： 一种方法包括在半导体本体中形成沟槽电容器。 在电容器的上部形成凹部，在半导体本体中具有侧壁。 第一材料沉积在凹槽的侧壁和底部上方。 第二种材料沉积在第一种材料上。 在第二材料上提供掩模。 掩模具有：掩蔽区域，以覆盖所述凹部底部的一部分; 以及位于所述凹陷侧壁的一部分上的窗口和所述凹陷底部的另一部分以暴露第二材料的下部。 第二材料的暴露下面的部分的部分是选择性地去除，同时留下第一材料的基本上未蚀刻的暴露的下部。 选择性地去除半导体主体的第一材料和下部的暴露部分。 在半导体本体的去除部分中形成隔离区。 所述掩模设置在所述第二材料上方，具有覆盖所述凹陷侧壁的一部分和所述凹部底部的一部分的掩蔽区域，以及设置在所述凹部侧壁的相对部分上方的窗口和所述凹部底部的相对部分， 第二材料的部分。 在半导体本体的暴露的下部设置蚀刻，以在半导体本体中形成浅沟槽。 在浅沟槽中形成绝缘材料以形成浅沟槽隔离区域。 通过这种方法，允许更大的掩模未对准公差。

公开(公告)号：EP0910117A2

公开(公告)日：1999-04-21

申请号：EP98305084.0

申请日：1998-06-26

申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

发明人： Levy, Max G. ,  Fiegl, Bernhard ,  Bergner, Wolfgang ,  Goth, George R. ,  Parries, Paul ,  Sendelbach, Matthew J. ,  Wang, Ting-Hao ,  Wille, William C. ,  Wittmann, Juergen

IPC分类号： H01L21/3105

CPC分类号： H01L21/31053

摘要： A method for preventing CMP-induced (chemical-mechanical polish) damage to a substrate disposed below a pad nitride layer of a mesa. The pad nitride layer is disposed below a conformally deposited dielectric layer. The dielectric layer is disposed below a conformally deposited polysilicon layer. The method includes planarizing the polysilicon layer down to at least a surface of the dielectric layer using the CMP to expose a first region of the dielectric layer. The method further includes etching partially through the first region of the dielectric layer using first etch parameters. The first etch parameters include an etchant source gas that is substantially selective to the pad nitride layer to prevent the pad nitride layer from being etched through even in the presence of a CMP defect. Additionally, there is also included removing the polysilicon layer after the etching partially through the first region of the dielectric layer.

摘要翻译： 一种用于防止对下方设置一个台面的衬垫氮化物层上的基材的CMP引起的（化学机械抛光）损伤的方法。 垫氮化物层被设置在共形地沉积介电层的下方。 所述介电层设置下方的共形沉积多晶硅层。 该方法包括：平坦化所述多晶硅层至至少使用CMP以暴露电介质层的第一区域中的电介质层的表面上。 该方法包括：通过使用第一蚀刻参数的电介质层的第一区域进行蚀刻进一步部分。 第一蚀刻参数包括蚀刻源气体的缺陷确实基本上选择性的衬垫氮化物层，以防止垫氮化物层从即使在CMP的情况下，通过被蚀刻。 此外，还有被包含因此部分地穿过介电层的第一区域中去除蚀刻后的多晶硅层。

公开(公告)号：EP0910117B1

公开(公告)日：2002-09-04

申请号：EP98305084.0

申请日：1998-06-26

申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

发明人： Levy, Max G. ,  Fiegl, Bernhard ,  Bergner, Wolfgang ,  Goth, George R. ,  Parries, Paul ,  Sendelbach, Matthew J. ,  Wang, Ting-Hao ,  Wille, William C. ,  Wittmann, Juergen

IPC分类号： H01L21/3105 ,  H01L21/321

CPC分类号： H01L21/31053

公开(公告)号：EP0910117A3

公开(公告)日：1999-06-02

申请号：EP98305084.0

申请日：1998-06-26

申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

发明人： Levy, Max G. ,  Fiegl, Bernhard ,  Bergner, Wolfgang ,  Goth, George R. ,  Parries, Paul ,  Sendelbach, Matthew J. ,  Wang, Ting-Hao ,  Wille, William C. ,  Wittmann, Juergen

IPC分类号： H01L21/3105

CPC分类号： H01L21/31053

摘要： A method for preventing CMP-induced (chemical-mechanical polish) damage to a substrate disposed below a pad nitride layer of a mesa. The pad nitride layer is disposed below a conformally deposited dielectric layer. The dielectric layer is disposed below a conformally deposited polysilicon layer. The method includes planarizing the polysilicon layer down to at least a surface of the dielectric layer using the CMP to expose a first region of the dielectric layer. The method further includes etching partially through the first region of the dielectric layer using first etch parameters. The first etch parameters include an etchant source gas that is substantially selective to the pad nitride layer to prevent the pad nitride layer from being etched through even in the presence of a CMP defect. Additionally, there is also included removing the polysilicon layer after the etching partially through the first region of the dielectric layer.

摘要翻译： 一种用于防止CMP引起的（化学机械抛光）损坏设置在台面的垫氮化物层下方的衬底的方法。 垫氮化物层设置在共形沉积的电介质层下方。 介电层设置在共形沉积的多晶硅层下方。 该方法包括使用CMP将多晶硅层平坦化到至少介电层的表面以暴露介电层的第一区域。 该方法还包括使用第一蚀刻参数部分地蚀刻介电层的第一区域。 第一蚀刻参数包括对衬垫氮化物层基本上具有选择性的蚀刻剂源气体，以防止衬垫氮化物层即使在存在CMP缺陷的情况下也被蚀刻穿过。 此外，还包括在蚀刻之后部分地通过介电层的第一区域去除多晶硅层。