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1.发明公开INTEGRATED CIRCUIT INCLUDING MEMORY ARRAY HAVING A SEGMENTED BIT LINE ARCHITECTURE AND METHOD OF CONTROLLING AND/OR OPERATING SAME 审中-公开用于控制和/或业务存储器阵列和分段位线的体系结构和方法集成电路
公开(公告)号：EP2041752A2
公开(公告)日：2009-04-01
申请号：EP07810300.9
申请日：2007-07-10
发明人： FISCH, David , BRON, Michel
CPC分类号： H01L27/108 , G11C7/12 , G11C7/18 , G11C11/4097 , G11C2207/002 , G11C2211/4016 , H01L27/10802 , H01L29/7841
摘要： An integrated memory circuit device having a memory cell array (102) including a plurality of bit lines (e.g., 32a, 32b) and a plurality of bit line segments (e.g., 32a1, 32b1) wherein each bit line segment is coupled to an associated bit line (32a, 32b). The memory cell array (102) further includes a plurality of memory cells (12), wherein each memory cell (12) includes a transistor (14) having a first region, a second region, a body region, and a gate coupled to an associated word line (28) via an associated word line segment. A first group of memory cells (12) is coupled to the first bit line (32a) via the first bit line segment (32a1) and a second group of memory cells (12) is coupled to the second bit line (32b) via the second bit line segment (32b1). A plurality of isolation circuits (104), disposed between each bit line segment (32a1, 32b1) and its associated bit line (32a, 32b), responsively connect the associated bit line segment to or disconnect the associated bit line segment (32a1, 32b1) from the associated bit line (32a, 32b).
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