公开(公告)号：EP3346474A1

公开(公告)日：2018-07-11

申请号：EP17181462.7

申请日：2017-07-14

申请人： eMemory Technology Inc.

发明人： PO, Chen-Hao ,  CHANG, Wu-Chang

IPC分类号： G11C16/12 ,  G11C7/04 ,  G11C7/10

CPC分类号： G11C16/14 ,  G11C7/04 ,  G11C7/1084 ,  G11C7/109 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/12 ,  G11C16/26 ,  G11C16/3472 ,  H01L27/11524 ,  H01L27/11541 ,  H01L27/11558 ,  H01L29/42328 ,  H01L29/42364 ,  H01L29/7841 ,  H01L29/7883 ,  H03K17/0828 ,  H03K19/088

摘要： A driving circuit includes a first driver, a switching circuit and a second driver. The first driver receives an input signal and an inverted input signal, and generates a driving signal. The switching circuit receives the driving signal and a first mode signal. Moreover, an output signal is outputted from an output terminal. The second driver is connected with the output terminal.

公开(公告)号：EP2866250A4

公开(公告)日：2016-09-28

申请号：EP13806624

申请日：2013-06-05

申请人： NAT INST OF ADVANCED IND SCIEN

发明人： NAKAJIMA AKIRA ,  NISHIZAWA SHINICHI ,  OHASHI HIROMICHI

IPC分类号： H01L29/778 ,  H01L27/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/423 ,  H01L29/47 ,  H01L29/78 ,  H01L29/808 ,  H01L29/872

CPC分类号： H01L27/0266 ,  H01L21/0455 ,  H01L21/049 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/04 ,  H01L29/045 ,  H01L29/1066 ,  H01L29/1075 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41725 ,  H01L29/4236 ,  H01L29/475 ,  H01L29/66068 ,  H01L29/7787 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7841 ,  H01L29/8083 ,  H01L29/872

摘要： [Problem] A wide band gap semiconductor device used in a power converter is known to have a problem that the device is destroyed with a high surge voltage, and tolerance against breakdown needs to be improved. This problem is known to be more outstanding in a unipolar and lateral type semiconductor device. [Solution] The present invention provides a semiconductor device that prevents destruction due to an avalanche breakdown and that has a high tolerance against breakdown by configuring the device so as to have a punch-through breakdown function therein and such that the breakdown voltage of a punch-through breakdown is lower than an avalanche breakdown voltage so that an avalanche breakdown does not occur.

公开(公告)号：EP2737524A4

公开(公告)日：2015-06-17

申请号：EP12818435

申请日：2012-07-18

申请人： MICRON TECHNOLOGY INC

发明人： BEIGEL KURT D ,  TANG SAHN D

IPC分类号： H01L21/8247 ,  H01L27/102 ,  H01L27/108 ,  H01L27/115 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786 ,  H01L29/788

CPC分类号： H01L29/0638 ,  H01L27/1027 ,  H01L27/10802 ,  H01L29/0688 ,  H01L29/7841 ,  H01L29/78642 ,  H01L29/7889

公开(公告)号：EP2543069A2

公开(公告)日：2013-01-09

申请号：EP11751050.3

申请日：2011-02-10

申请人： Micron Technology, Inc.

发明人： TANG, Sanh, D. ,  ZHANG, Ming ,  BAYLESS, Andrew, M. ,  ZAHURAK, John, K.

IPC分类号： H01L27/12 ,  H01L21/20 ,  H01L27/115 ,  H01L21/8247

CPC分类号： H01L27/1203 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/30604 ,  H01L21/76251 ,  H01L21/76254 ,  H01L21/84 ,  H01L27/1021 ,  H01L27/10802 ,  H01L27/12 ,  H01L27/24 ,  H01L29/04 ,  H01L29/16 ,  H01L29/7841 ,  H01L29/78603 ,  H01L29/78642 ,  H01L29/78645 ,  H01L29/78648

摘要： Methods for fabricating semiconductor-metal-on-insulator (SMOI) structures include forming an acceptor wafer including an insulator material on a first semiconductor substrate, forming a donor wafer including a conductive material and an amorphous silicon material on a second semiconductor substrate, and bonding the amorphous silicon material of the donor wafer to the insulator material of the acceptor wafer. SMOI structures formed from such methods are also disclosed, as are semiconductor devices including such SMOI structures.

公开(公告)号：EP2474038A1

公开(公告)日：2012-07-11

申请号：EP10760154.4

申请日：2010-09-01

申请人： Qualcomm Incorporated

发明人： SONG, Seung-Chul ,  ABU-RAHMA, Mohamed, Hassan ,  HAN, Beom-Mo

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/785 ,  G11C11/40 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7841 ,  H01L29/7855 ,  H01L29/78648

摘要： A method includes forming a gate of a transistor within a substrate having a surface and forming a buried oxide (BOX) layer within the substrate and adjacent to the gate at a first BOX layer face. The method also includes forming a raised source-drain channel (“fin”), where at least a portion of the fin extends from the surface of the substrate, and where the fin has a first fin face adjacent a second BOX layer face of the BOX layer.

摘要翻译： 一种方法包括在具有表面的衬底内形成晶体管的栅极，并在衬底内形成掩埋氧化物（BOX）层，并在第一BOX层面与栅极相邻。 该方法还包括形成升高的源极 - 漏极通道（“鳍”），其中鳍的至少一部分从衬底的表面延伸，并且其中鳍具有邻近第二BOX层的第一鳍面 BOX层。

公开(公告)号：EP2284879A4

公开(公告)日：2012-05-23

申请号：EP09738995

申请日：2009-04-30

申请人： IUCF HYU

发明人： PARK JEA-GUN ,  SHIM TAE-HUN ,  LEE GON-SUB ,  KIM SEONG-JE ,  KIM TAE-HYUN

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L29/4234 ,  G11C11/404 ,  G11C16/0466 ,  G11C2211/4016 ,  H01L27/10802 ,  H01L29/7841 ,  H01L29/78687 ,  H01L29/78696

摘要： Provided is a capacitorless memory device. The device includes a semiconductor substrate, an insulating layer disposed on the semiconductor substrate, a storage region disposed on a partial region of the insulating layer, a channel region disposed on the storage region to provide a valence band energy offset between the channel region and the storage region, a gate insulating layer and a gate electrode sequentially disposed on the channel region, and source and drain electrodes connected to the channel region and disposed at both sides of the gate electrode. A storage region unit having different valence band energy from a channel region unit is disposed under the channel region unit so that charges trapped in the storage region unit cannot be easily drained. Thus, a charge retention time may be increased to improve data storage capability.

公开(公告)号：EP2206143A4

公开(公告)日：2012-04-18

申请号：EP08841399

申请日：2008-09-19

申请人： MICRON TECHNOLOGY INC

发明人： LIU JUN ,  LI DI ,  VIOLETTE MICHAEL P ,  MOULI CHANDRA ,  KIRSH HOWARD

IPC分类号： H01L29/78 ,  H01L27/108

CPC分类号： H01L27/1203 ,  H01L27/10802 ,  H01L29/66477 ,  H01L29/7841 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor SixGe(1-x)-comprising region. The floating body channel region has a semiconductor silicon-comprising region received between the semiconductor SixGe(1-x)-comprising region and the gate dielectric. The semiconductor SixGe(1-x)-comprising region has greater quantity of Ge than any quantity of Ge within the semiconductor silicon-comprising region. Other embodiments are contemplated, including methods of forming floating body field-effect transistors.

公开(公告)号：EP2333779A1

公开(公告)日：2011-06-15

申请号：EP10187012.9

申请日：2010-10-08

申请人： S.O.I.Tec Silicon on Insulator Technologies

发明人： Mazure, Carlos ,  Ferrant, Richard

IPC分类号： G11C11/404 ,  H01L27/108 ,  H01L29/423 ,  H01L29/78

CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/42356 ,  H01L29/7841

摘要： The invention relates to a method of controlling a DRAM memory cell consisting of an FET transistor on a semiconductor-on-insulator substrate comprising a thin film (3) of semiconductor material separated from a base substrate (1) by an insulating layer (2, BOX), the transistor having a channel (4) and two control gates, a front control gate (8, 11) being arranged on top of the channel (4) and separated from the latter by a gate dielectric (7, 10) and a back control gate (9, 12, 13, 17, 18) being arranged in the base substrate and separated from the channel (4) by the insulating layer (BOX), characterized in that, in a cell programming operation, the front control gate and the back control gate are used jointly by applying a first voltage to the front control gate and a second voltage to the back control gate, said first voltage being lower in amplitude than the voltage needed to program the cell when no voltage is applied to the back control gate.

摘要翻译： 本发明涉及（2控制DRAM存储器单元的FET晶体管的在包括半导体材料的薄膜（3）在绝缘层通过从基底基板（1）分离的半导体在绝缘体上的基板组成的方法， BOX），被布置成具有一个信道（4）和两个控制栅，一个前控制栅极（8，11）中的晶体管上的通道（4）的顶部，并通过栅极电介质（7从后者分离，10）和 背控制栅（9，12，13，17，18）被布置在所述基底基板，并且从通道（4）通过绝缘层（BOX），在该特点是，在一个单元编程操作，前控制分离 栅极和后控制栅极被施加第一电压施加到所述前控制栅极和一个第二电压施加到背控制栅极共同使用时，所述第一电压在幅度上比所述单元编程所需的电压是低级当没有电压被施加到 背控制栅极。

公开(公告)号：EP1918998A3

公开(公告)日：2009-09-30

申请号：EP07019404.8

申请日：2007-10-04

申请人： Samsung Electronics Co., Ltd.

发明人： Tak, Nam-Kyun ,  Song, Ki-Whan ,  Oh, Chang-Woo ,  Cho, Woo-Yeong

IPC分类号： H01L29/78 ,  H01L27/108 ,  H01L21/336

CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/7834 ,  H01L29/7841

摘要： A single transistor floating-body dynamic random access memory (DRAM) device structure includes a floating body (55) located on a semiconductor substrate (51) and a gate electrode (63) located on the floating body, the floating body including an excess carrier storage region (55S). The DRAM device further includes source and drain regions (73) respectively located at both sides of the gate electrode, and leakage shielding patterns (71') located between the floating body and the source and drain regions. Each of the source and drain regions contact the floating body.

公开(公告)号：EP1987520A4

公开(公告)日：2009-07-29

申请号：EP07750961

申请日：2007-02-15

申请人： INNOVATIVE SILICON ISI SA

发明人： CARMAN ERIC ,  OKHONIN SERGUEI ,  JONES MARK-ERIC

IPC分类号： G11C11/404 ,  G11C7/10 ,  G11C7/16 ,  G11C11/4076 ,  G11C11/56 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L29/7841 ,  G11C7/1006 ,  G11C7/16 ,  G11C11/404 ,  G11C11/565 ,  G11C2211/4016

摘要： Multi-bit memory cell and circuitry and techniques for reading, writing and/or operating a multi-bit memory cell (and memory cell array having a plurality of such memory cells) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The multi-bit memory cell stores more than one data bit (for example, two, three, four, five, six, etc ) and/or more than two data states (for example, three, four, five, six, etc. data or logic states. Notably, the memory cell array may comprise a portion of an integrated circuit device, for example, logic device (for example, a microprocessor) or a portion of a memory device (for example, a discrete memory)