公开(公告)号：EP4109240A1

公开(公告)日：2022-12-28

申请号：EP22160487.9

申请日：2022-03-07

申请人： Intel Corporation

发明人： PAL, Supratim ,  FEGHALI, Wajdi ,  RHEE, Changwon ,  CHEN, Wei-Yu ,  BAUER, Timothy R. ,  LYASHEVSKY, Alexander

IPC分类号： G06F9/30 ,  G06F9/38 ,  H04L9/06

摘要： An apparatus to facilitate a fused instruction to accelerate performance of secure hash algorithm 2 (SHA-2) in a graphics environment is disclosed. The apparatus includes a processor comprising processing resources, the processing resources comprising execution circuitry to receive a fused SHA instruction identifying a length corresponding to a data size of the fused SHA instruction and a functional control identifying an operation type of the fused SHA instruction; based on decoding the fused SHA instruction, cause a sub-function identified by the length and the function control to be scheduled to an integer pipeline of the execution resource; and execute the sub-function of the fused SHA instruction in an integer pipeline of the execution circuitry, the sub-function to perform merged operations on a source operand of the fused SHA instruction, the merged operations comprising a rotate operation, a shift operation, and an xor operation.