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    METHOD AND APPARATUS FOR PERFORMING MODULAR EXPONENTIATIONS
    4.
    发明公开
    METHOD AND APPARATUS FOR PERFORMING MODULAR EXPONENTIATIONS 有权
    方法及装置实现模块化potentisations的

    公开(公告)号：EP1789869A2

    公开(公告)日：2007-05-30

    申请号：EP05818313.8

    申请日：2005-09-02

    申请人： INTEL CORPORATION

    发明人： KOSHY, Kamal ,  WOLRICH, Gilbert ,  SYDIR, Jaroslaw ,  FEGHALI, Wajdi

    IPC分类号： G06F7/72

    CPC分类号： G06F7/728

    摘要： An arrangement is provided for performing modular exponentiations. A modular exponentiation may be performed by using multiple Montgomery multiplications. A Montgomery multiplication comprises a plurality of iterations of basic operations (e.g., carry-save additions), and is performed by a Montgomery multiplication engine (MME). Multiple MMEs of smaller sizes may be chained together to perform modular exponentiations of larger sizes. Additionally, a single MME of a smaller size may be scheduled to perform modular exponentiations of larger sizes. Moreover, the process of performing a Montgomery multiplication may be pipelined both horizontally and vertically. Furthermore, processes of performing two Montgomery multiplications may be interleaved and performed by the same MME or chained MMEs.

    FILTER FOR NETWORK INTRUSION AND VIRUS DETECTION
    5.
    发明公开
    FILTER FOR NETWORK INTRUSION AND VIRUS DETECTION 审中-公开
    过滤器，用于检测NETZWERKEINDRINGUNG和病毒

    公开(公告)号：EP2382739A2

    公开(公告)日：2011-11-02

    申请号：EP09836863.2

    申请日：2009-12-16

    申请人： Intel Corporation

    发明人： GOPAL, Vinodh ,  CLARK, Christopher, F. ,  WOLRICH, Gilbert ,  FEGHALI, Wajdi

    IPC分类号： H04L12/26 ,  G06F21/20

    CPC分类号： H04L63/145 ,  G06F7/02 ,  G06F17/30949 ,  G06F17/30985 ,  G06F21/567 ,  G06F2207/025 ,  H04L63/0245 ,  H04L63/1416

    摘要： Methods and apparatus to perform string matching for network packet inspection are disclosed. In some embodiments there is a set of string matching slice circuits, each slice circuit of the set being configured to perform string matching steps in parallel with other slice circuits. Each slice circuit may include an input window storing some number of bytes of data from an input data steam. The input window of data may be padded if necessary, and then multiplied by a polynomial modulo an irreducible Galois-field polynomial to generate a hash index. A storage location of a memory corresponding to the hash index may be accessed to generate a slice-hit signal of a set of H slice-hit signals. The slice-hit signal may be provided to an AND-OR logic array where the set of H slice-hit signals is logically combined into a match result.

    METHOD FOR PROCESSING MULTIPLE OPERATIONS
    6.
    发明公开
    METHOD FOR PROCESSING MULTIPLE OPERATIONS 审中-公开
    一种用于处理多个操作

    公开(公告)号：EP2126688A1

    公开(公告)日：2009-12-02

    申请号：EP07854971.4

    申请日：2007-12-05

    申请人： Intel Corporation

    发明人： FEGHALI, Wajdi ,  HIRNAK, Stephanie ,  RAGHUNANDAN, Makaram ,  BANSAL, Yogesh ,  YAP, Kirk ,  WOLRICH, Gilbert, M

    IPC分类号： G06F9/06 ,  G06F9/46 ,  G06F12/08

    CPC分类号： H04L63/0485 ,  G06F9/30181 ,  G06F9/3879 ,  H04L63/08

    摘要： In one embodiment, the present disclosure provides a method capable of processing a variety of different operations. A method according to one embodiment may include loading configuration data from a shared memory unit into a hardware configuration register, the hardware configuration register located within circuitry included within a hardware accelerator unit. The method may also include issuing a command set from a microengine to the hardware accelerator unit having the circuitry. The method may additionally include receiving the command set at the circuitry from the microengine, the command set configured to allow for the processing of a variety of different operations. The method may further include processing an appropriate operation based upon the configuration data loaded into the hardware configuration register. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

    FUSED INSTRUCTION TO ACCELERATE PERFORMANCE OF SECURE HASH ALGORITHM 2 (SHA-2) WORKLOADS IN A GRAPHICS ENVIRONMENT
    8.
    发明公开
    FUSED INSTRUCTION TO ACCELERATE PERFORMANCE OF SECURE HASH ALGORITHM 2 (SHA-2) WORKLOADS IN A GRAPHICS ENVIRONMENT 审中-公开

    公开(公告)号：EP4109240A1

    公开(公告)日：2022-12-28

    申请号：EP22160487.9

    申请日：2022-03-07

    申请人： Intel Corporation

    发明人： PAL, Supratim ,  FEGHALI, Wajdi ,  RHEE, Changwon ,  CHEN, Wei-Yu ,  BAUER, Timothy R. ,  LYASHEVSKY, Alexander

    IPC分类号： G06F9/30 ,  G06F9/38 ,  H04L9/06

    摘要： An apparatus to facilitate a fused instruction to accelerate performance of secure hash algorithm 2 (SHA-2) in a graphics environment is disclosed. The apparatus includes a processor comprising processing resources, the processing resources comprising execution circuitry to receive a fused SHA instruction identifying a length corresponding to a data size of the fused SHA instruction and a functional control identifying an operation type of the fused SHA instruction; based on decoding the fused SHA instruction, cause a sub-function identified by the length and the function control to be scheduled to an integer pipeline of the execution resource; and execute the sub-function of the fused SHA instruction in an integer pipeline of the execution circuitry, the sub-function to perform merged operations on a source operand of the fused SHA instruction, the merged operations comprising a rotate operation, a shift operation, and an xor operation.