公开(公告)号：EP4354348A1

公开(公告)日：2024-04-17

申请号：EP23190370.9

申请日：2023-08-08

申请人： Intel Corporation

发明人： POWER, Martin ,  BYRNE, Conor ,  HANRAHAN, Niall ,  MATHAIKUTTY, Deepak Abraham ,  RAHA, Arnab ,  SUNG, Raymond Jit-Hung ,  BERNARD, David Thomas ,  BRADY, Kevin ,  GRYMEL, Martin-Thomas

IPC分类号： G06N3/0495 ,  G06N3/063 ,  G06N3/0464

CPC分类号： G06N3/0464 ,  G06N3/0495 ,  G06N3/063

摘要： Sparsity processing within a compute block can be done on unpacked data. The compute block includes a sparsity decoder that generates a combined sparsity vector from an activation sparsity vector and a weight sparsity vector. The activation sparsity vector indicates positions of non-zero valued activations in an activation context. The weight sparsity vector indicates positions of non-zero valued weights in a weight context. The combined sparsity vector comprises one or more zero valued bits and one or more non-zero valued bits. The sparsity decoder may determine the position of a non-zero valued bit in the combined sparsity vector and determine an address for the non-zero valued activation and the non-zero valued weight based on the position of the non-zero valued bit. The non-zero valued activation and the non-zero valued weight may be provided to a PE for performing MAC operations.

公开(公告)号：EP4343565A1

公开(公告)日：2024-03-27

申请号：EP23183425.0

申请日：2023-07-04

申请人： INTEL Corporation

发明人： SUNG, Raymond Jit-Hung ,  MATHAIKUTTY, Deepak Abraham ,  AGARWAL, Amit ,  BERNARD, David Thomas ,  HSU, Steven ,  POWER, Martin ,  BYRNE, Conor ,  RAHA, Arnab

IPC分类号： G06F15/167 ,  G06N3/0464 ,  G06N3/063 ,  G06N3/084 ,  G11C11/54

摘要： A memory array of a compute tile may store activations or weights of a DNN. The memory array may include databanks for storing contexts, context MUXs, and byte MUXs. A databank may store a context with flip-flop arrays, each of which includes a sequence of flip-flops. A logic gate and an ICG unit may gate flip-flops and control whether states of the flip-flops can be changed. The data gating can prevent a context not selected for the databank from inadvertently toggling and wasting power A context MUX may read a context from different flip-flop arrays in a databank based on gray-coded addresses. A byte MUX can combine bits from different bytes in a context read by the context MUX. The memory array may be implemented with bit packing to reduce distance between the context MUX and byte MUX to reduce lengths of wires connecting the context MUXs and byte MUXs.