公开(公告)号：EP4328802A1

公开(公告)日：2024-02-28

申请号：EP23186330.9

申请日：2023-07-19

申请人： INTEL Corporation

发明人： RAHA, Arnab ,  CHEEMA, Umer Iftikhar ,  GUPTA, Praveen Kumar ,  MATHAIKUTTY, Deepak Abraham ,  SUNG, Raymond Jit-Hung

IPC分类号： G06N3/063 ,  G06N3/0464 ,  G06N3/048 ,  G06N3/09

摘要： An DNN accelerator includes one or more heterogenous tile sets. A heterogenous tile set includes tiles of different sizes, e.g., PE arrays including different numbers of columns or rows. The DNN accelerator may identify a tile set from the tile sets for running a DNN model based on dimensions of output tensors convolutional layers in the DNN. Within the selected tile set, a tile may be selected for a convolutional layer in the DNN, e.g., based on dimensions of the output tensor of the convolutional layer and the size of the tile. After the tile is selected, the workload for running a convolutional operation of the layer may be partitioned and assigned to individual PEs in the tile by partitioning the output tensor into output tensor segments. The workload of computing an individual output tensor segment can be assigned to an individual PE in the tile.

公开(公告)号：EP4109345A1

公开(公告)日：2022-12-28

申请号：EP22164591.4

申请日：2022-03-25

申请人： Intel Corporation

发明人： CHINYA, Gautham ,  MATHAIKUTTY, Deepak ,  MOHAPATRA, Debabrata ,  KIM, Sang Kyun ,  RAHA, Arnab ,  BRICK, Cormac

IPC分类号： G06N3/04 ,  G06N3/063 ,  H03K19/20 ,  H03K19/177 ,  G06F7/544

摘要： Methods, apparatus, systems, and articles of manufacture to load data into an accelerator are disclosed. An example apparatus includes data provider circuitry to load a first section and an additional amount of compressed machine learning parameter data into a processor engine. Processor engine circuitry executes a machine learning operation using the first section of compressed machine learning parameter data. A compressed local data re-user circuitry determines if a second section is present in the additional amount of compressed machine learning parameter data. The processor engine circuitry executes a machine learning operation using the second section when the second section is present in the additional amount of compressed machine learning parameter data.

公开(公告)号：EP4437456A1

公开(公告)日：2024-10-02

申请号：EP22899259.0

申请日：2022-10-14

申请人： Intel Corporation

发明人： RAHA, Arnab ,  MOHAPATRA, Debabrata ,  MATHAIKUTTY, Deepak Abraham ,  SUNG, Raymond Jit-Hung ,  BRICK, Cormac Michael

IPC分类号： G06N3/04 ,  G06F7/76

CPC分类号： G06F2207/482420130101 ,  G06F7/76 ,  G06F7/5443 ,  G06N3/08 ,  G06N3/063 ,  G06N3/048 ,  G06N3/045

公开(公告)号：EP4357978A1

公开(公告)日：2024-04-24

申请号：EP23191148.8

申请日：2023-08-11

申请人： INTEL Corporation

发明人： MATHAIKUTTY, Deepak Abraham ,  RAHA, Arnab ,  SUNG, Raymond Jit-Hung ,  POWER, Martin ,  CHEEMA, Umer Iftikhar ,  BERNARD, David Thomas

IPC分类号： G06N3/0464 ,  G06N3/048 ,  G06N3/0495 ,  G06N3/063

CPC分类号： G06N3/0464 ,  G06N3/0495 ,  G06N3/063 ,  G06N3/048

摘要： An DNN accelerator may include a PE array performing MAC operations. The PE array may include PEs capable of MAC operations on quantized values. A PE may include subtractors for subtracting zeropoints from quantized activations and quantized weights to generate intermediate activations and intermediate weights. The intermediate activations and intermediate weights may be stored in data storage units in the PE and maybe used by an MAC unit in the PE. The subtractors may be placed outside the MAC unit but inside the PE. The MAC unit may perform sequential cycles of MAC operations. The MAC unit may include a plurality of multipliers. The intermediate activations and intermediate weights stored in the data storage units may be reused by different multipliers in different cycles of MAC operations. An output of the MAC unit or of the PE may be multiplied with a quantization scale to produce a floating-point value.

公开(公告)号：EP4343565A1

公开(公告)日：2024-03-27

申请号：EP23183425.0

申请日：2023-07-04

申请人： INTEL Corporation

发明人： SUNG, Raymond Jit-Hung ,  MATHAIKUTTY, Deepak Abraham ,  AGARWAL, Amit ,  BERNARD, David Thomas ,  HSU, Steven ,  POWER, Martin ,  BYRNE, Conor ,  RAHA, Arnab

IPC分类号： G06F15/167 ,  G06N3/0464 ,  G06N3/063 ,  G06N3/084 ,  G11C11/54

摘要： A memory array of a compute tile may store activations or weights of a DNN. The memory array may include databanks for storing contexts, context MUXs, and byte MUXs. A databank may store a context with flip-flop arrays, each of which includes a sequence of flip-flops. A logic gate and an ICG unit may gate flip-flops and control whether states of the flip-flops can be changed. The data gating can prevent a context not selected for the databank from inadvertently toggling and wasting power A context MUX may read a context from different flip-flop arrays in a databank based on gray-coded addresses. A byte MUX can combine bits from different bytes in a context read by the context MUX. The memory array may be implemented with bit packing to reduce distance between the context MUX and byte MUX to reduce lengths of wires connecting the context MUXs and byte MUXs.

公开(公告)号：EP4330860A1

公开(公告)日：2024-03-06

申请号：EP22796343.6

申请日：2022-03-21

申请人： Intel Corporation

发明人： RAHA, Arnab ,  MOHAPATRA, Debabrata ,  CHINYA, Gautham ,  VENKATARAMANAN, Guruguhanathan ,  KIM, Sang Kyun ,  MATHAIKUTTY, Deepak ,  SUNG, Raymond ,  BRICK, Cormac

IPC分类号： G06N3/063 ,  G06N3/04

公开(公告)号：EP4109236A1

公开(公告)日：2022-12-28

申请号：EP22164550.0

申请日：2022-03-25

申请人： INTEL Corporation

发明人： KRISHNAMURTHY, Ram ,  ANDERS, Mark ,  KAUL, Himanshu ,  CHINYA, Gautham ,  POWER, Martin ,  MOHAPATRA, Debabrata ,  RAHA, Arnab ,  LANGHAMMER, Martin ,  BRICK, Cormac

IPC分类号： G06F7/53

摘要： Systems, apparatuses and methods may provide for multi-precision multiply-accumulate (MAC) technology that includes a plurality of arithmetic blocks, wherein the plurality of arithmetic blocks each contain multiple multipliers, and wherein the logic is to combine multipliers one or more of within each arithmetic block or across multiple arithmetic blocks. In one example, one or more intermediate multipliers are of a size that is less than precisions supported by arithmetic blocks containing the one or more intermediate multipliers.

公开(公告)号：EP4433897A1

公开(公告)日：2024-09-25

申请号：EP22896300.5

申请日：2022-10-14

申请人： Intel Corporation

发明人： MOHAPATRA, Debabrata ,  RAHA, Arnab ,  MATHAIKUTTY, Deepak Abraham ,  SUNG, Raymond Jit-Hung ,  BRICK, Cormac Michael

IPC分类号： G06F9/50 ,  G06N3/04 ,  G06F9/30 ,  G06F7/544

CPC分类号： G06F7/5443 ,  G06F2207/482420130101 ,  G06F9/3012 ,  G06N3/063 ,  G06N3/084 ,  G06N3/048 ,  G06N3/045

公开(公告)号：EP4430525A1

公开(公告)日：2024-09-18

申请号：EP22893750.4

申请日：2022-09-24

申请人： Intel Corporation

发明人： MATHAIKUTTY, Deepak ,  RAHA, Arnab ,  SUNG, Raymond ,  MOHAPATRA, Debabrata ,  BRICK, Cormac

IPC分类号： G06N3/08 ,  G06N5/04

CPC分类号： G06N3/063 ,  G06N3/04

公开(公告)号：EP4427132A1

公开(公告)日：2024-09-11

申请号：EP22890594.9

申请日：2022-10-04

申请人： Intel Corporation

发明人： MOHAPATRA, Debabrata ,  RAHA, Arnab ,  MATHAIKUTTY, Deepak ,  SUNG, Raymond ,  BRICK, Cormac

IPC分类号： G06F9/50 ,  G06F9/48 ,  G06N20/00 ,  G06F15/80 ,  G06F7/50

CPC分类号： G06F2207/482420130101 ,  G06F7/485 ,  G06N3/063 ,  G06F15/7867 ,  G06N3/045