专利检索 ap:("Intel Corporation") AND inv:"GURRAM, Chandra" 第 1 页

1.

发明公开
DUAL PIPELINE PARALLEL SYSTOLIC ARRAY 审中-实审

公开(公告)号：EP4359919A1

公开(公告)日：2024-05-01

申请号：EP22714700.6

申请日：2022-03-16

申请人： Intel Corporation

发明人： PARRA, Jorge , CHEN, Jiasheng , PAL, Supratim , FU, Fangwen , GANAPATHY, Sabareesh , GURRAM, Chandra , MEI, Chunhui , QI, Yue

IPC分类号： G06F9/30 , G06F9/38 , G06F17/16 , G06F15/80

CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30036 , G06F9/3893 , G06F9/3828 , G06F17/16 , G06F15/8046

2.

发明公开
SYSTOLIC ARRAY OF ARBITRARY PHYSICAL AND LOGICAL DEPTH 审中-实审

公开(公告)号：EP4359920A1

公开(公告)日：2024-05-01

申请号：EP22717966.0

申请日：2022-03-17

申请人： INTEL Corporation

发明人： PARRA, Jorge , CHEN, Wei-yu , CHEN, Kaiyu , GEORGE, Varghese , GU, Junjie , GURRAM, Chandra , LUEH, Guei-Yuan , JUNKINS, Stephen , MAIYURAN, Subramaniam , PAL, Supratim

IPC分类号： G06F9/30

CPC分类号： G06F9/3001 , G06F9/30036 , G06F9/3016 , G06F15/8046

3.

发明公开
COMPACTION OF DIVERGED LANES FOR EFFICIENT USE OF ALUS 审中-公开

公开(公告)号：EP3907606A1

公开(公告)日：2021-11-10

申请号：EP20213794.9

申请日：2020-12-14

申请人： Intel Corporation

发明人： GURRAM, Chandra , MAIYURAN, Subramaniam , PAL, Supratim , SHARMA, Saurabh , NAVALE, Aditya

IPC分类号： G06F9/38

摘要： Described herein is an accelerator device in which compaction of diverged lanes of a parallel processor is enabled to increase the efficiency of ALU utilization. One embodiment provides an accelerator device comprising a host interface, a fabric interconnect coupled with the host interface, and one or more hardware tiles coupled with the fabric interconnect, the one or more hardware tiles including a parallel processing architecture configured to enable compaction of diverged lanes.

4.

发明公开
SYSTOLIC ARRAY HAVING SUPPORT FOR OUTPUT SPARSITY 审中-实审

公开(公告)号：EP4359967A1

公开(公告)日：2024-05-01

申请号：EP22717046.1

申请日：2022-03-15

申请人： Intel Corporation

发明人： PARRA, Jorge , FU, Fangwen , MAIYURAN, Subramaniam , GEORGE, Varghese , MACPHERSON, Mike , PAL, Supratim , GURRAM, Chandra , GANAPATHY, Sabareesh , AVANCHA, Sasikanth , VOOTURI, Dharma Teja , MELLEMPUDI, Naveen , DAS, Dipankar

IPC分类号： G06F17/16 , G06F9/00

CPC分类号： G06F17/16 , G06F15/8046 , G06F9/3001 , G06F9/30036

5.

发明公开
GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUCT ACCUMULATE INSTRUCTION FOR HYBRID FLOATING POINT FORMAT 审中-公开

公开(公告)号：EP3938891A1

公开(公告)日：2022-01-19

申请号：EP20718910.1

申请日：2020-03-14

申请人： Intel Corporation

发明人： MAIYURAN, Subramaniam , MARWAHA, Shubra , GARG, Ashutosh , PAL, Supratim , PARRA, Jorge , GURRAM, Chandra , GEORGE, Varghese , STARKEY, Darin , LUEH, Guei-Yuan

IPC分类号： G06F9/30