公开(公告)号：EP3809266A1

公开(公告)日：2021-04-21

申请号：EP20213160.3

申请日：2018-03-23

申请人： INTEL Corporation

发明人： APPU, Abhishek ,  KOKER, Altug ,  VEMBU, Balaji ,  RAY, Joydeep ,  SINHA, Kamal ,  SURTI, Prasoonkumar ,  VEERNAPU, Kiran C. ,  MAIYURAN, Subramaniam ,  JAHAGIRDAR, Sanjeev S. ,  ASPERHEIM, Eric J. ,  LUEH, Guei-Yuan ,  PUFFER, David ,  FU, Wenyin ,  KABURLASOS, Nikos ,  BOROLE, Bhushan M. ,  MASTRONARDE, Josh B. ,  HURD, Linda L. ,  SCHLUESSLER, Travis T. ,  JANCZAK, Tomasz ,  VENKATESH, Abhishek ,  XIAO, Kai ,  GRAJEWSKI, Slawomir

IPC分类号： G06F9/50

摘要： In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：EP3072048A1

公开(公告)日：2016-09-28

申请号：EP13898018.0

申请日：2013-11-22

申请人： Intel Corporation

发明人： CHEN, Weike ,  TANG, Li-An ,  LUEH, Guei-Yuan ,  YUAN, Hao ,  HSU, Samuel

IPC分类号： G06F9/46

CPC分类号： G06T1/20 ,  G06F9/4843 ,  G06F9/5016 ,  G06T2200/28

摘要： In an embodiment, at least one computer readable storage medium has instructions stored thereon for causing a system to send, from a processor to a task execution device, a first call to execute a first subroutine of a set of chained subroutines. The first subroutine may have a first subroutine output argument that includes a first token to indicate that first output data from execution of the first subroutine is intermediate data of the set of chained subroutines. The instructions are also for causing the system, responsive to inclusion of the first token in the first subroutine output argument, to enable the processor to execute one or more operations while the task execution device executes the first subroutine. Other embodiments are described and claimed.

公开(公告)号：EP3392828B1

公开(公告)日：2020-03-04

申请号：EP18168630.4

申请日：2018-04-20

申请人： INTEL Corporation

发明人： MAIYURAN, Subramaniam M. ,  LUEH, Guei-Yuan ,  PAL, Supratim ,  CHEN, Gang ,  KOMMARAJU, Ananda V. ,  CHANDRA, Joy ,  KOKER, Altug ,  SURTI, Prasoonkumar ,  PUFFER, David ,  LIAO, Hong Bin ,  RAY, Joydeep ,  APPU, Abhishek R. ,  SHAH, Ankur N. ,  SCHLUESSLER, Travis T. ,  KENNEDY, Jonathan ,  BURKE, Devan

IPC分类号： G06T1/20

公开(公告)号：EP3394748A1

公开(公告)日：2018-10-31

申请号：EP16879654.8

申请日：2016-11-17

申请人： Intel Corporation

发明人： VENKATESH, Jayashree ,  CHEN, Gang ,  RAOUX, Thomas F. ,  LUEH, Guei-Yuan ,  MAIYURAN, Maiyuran

IPC分类号： G06F9/48 ,  G06F9/38 ,  G06T15/80

CPC分类号： G06F9/38 ,  G06F9/30

摘要： Reducing SIMD fragmentation for SIMD execution widths of 32 or even 64 channels in a single hardware thread leads to better EU utilization. Increasing SIMD execution widths to 32 or 64 channels per thread, enables handling more vertices, patches, primitives and triangles per EU hardware thread. Modified 3D pipeline shader payloads can handle multiple patches in case of domain shaders or multiple primitives when primitive object instance count is greater than one in the case of geometry shaders and multiple triangles in case of pixel shaders.

公开(公告)号：EP1652094B1

公开(公告)日：2012-11-21

申请号：EP04778511.8

申请日：2004-07-16

申请人： Intel Corporation

发明人： GANSHA, Wu ,  LUEH, Guei-Yuan

IPC分类号： G06F12/02

CPC分类号： G06F12/0261 ,  G06F12/0269 ,  Y10S707/99944 ,  Y10S707/99957

公开(公告)号：EP2097808A1

公开(公告)日：2009-09-09

申请号：EP07869459.3

申请日：2007-12-18

申请人： Intel Corporation

发明人： LUEH, Guei-Yuan ,  JIANG, Hong ,  RIFFEL, Andrew T. ,  ZHENG, Bixia ,  LIM, Chu-Cheow ,  GIRKAR, Milind ,  SEHR, David C. ,  PIAZZA, Thomas A.

IPC分类号： G06F9/30 ,  G06F9/34

CPC分类号： G06F8/4434 ,  G06F8/447 ,  G06F9/30036 ,  G06F9/30156 ,  G06F9/30167 ,  G06F9/30178 ,  G06F9/3853

摘要： In some embodiments, a data structure may be received in a first processing system. The data structure may represent a plurality of instructions for a second processing system. For at least one instruction of the plurality of instructions, a determination may be made as to whether the instruction can be replaced by a compact instruction for the second processing system. A compact instruction may be generated if the instruction can be replaced by a compact instruction. In some embodiments, an instruction may be received in a processing system. A determination may be made as to whether the instruction is a compact instruction. A decompacted instruction may be generated if the instruction is a compact instruction.

公开(公告)号：EP1618474B1

公开(公告)日：2009-05-27

申请号：EP04760489.7

申请日：2004-03-19

申请人： Intel Corporation

发明人： WU, Gansha, Room 302, 1 unit ,  LUEH, Guei-Yuan ,  SHI, Xiaohua

IPC分类号： G06F9/46

CPC分类号： G06F9/52 ,  G06F8/458 ,  G06F9/449 ,  G06F9/45516

摘要： Apparatus and methods for desynchronizing object-oriented software applications in managed runtime environments are disclosed. Apparatus and methods for desynchronizing synchronized program code determine a type of the program code during just-in-time compilation of the program code and modify the program code during just-in-time compilation of the program code based on the type of the program code to desynchronize the program code.

公开(公告)号：EP3916550A1

公开(公告)日：2021-12-01

申请号：EP21184960.9

申请日：2018-03-30

申请人： Intel Corporation

发明人： KOKER, Altug ,  SURTI, Prasoonkumar ,  PUFFER, David ,  MAIYURAN, Subramaniam ,  LUEH, Guei-Yuan ,  APPU, Abhishek R. ,  RAY, Joydeep ,  VEMBU, Balaji ,  BAR-ON, Tomer ,  LAURITZEN, Andrew T. ,  LABBE, Hugues ,  GIERACH, John G. ,  LIKTOR, Gabor

IPC分类号： G06F9/46 ,  G06F9/48

摘要： In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

公开(公告)号：EP3392828A1

公开(公告)日：2018-10-24

申请号：EP18168630.4

申请日：2018-04-20

申请人： INTEL Corporation

发明人： MAIYURAN, Subramaniam M. ,  LUEH, Guei-Yuan ,  PAL, Supratim ,  CHEN, Gang ,  KOMMARAJU, Ananda V. ,  CHANDRA, Joy ,  KOKER, Altug ,  SURTI, Prasoonkumar ,  PUFFER, David ,  LIAO, Hong Bin ,  RAY, Joydeep ,  APPU, Abhishek R. ,  SHAH, Ankur N. ,  SCHLUESSLER, Travis T. ,  KENNEDY, Jonathan ,  BURKE, Devan

IPC分类号： G06T1/20

摘要： An apparatus to facilitate control flow in a graphics processing system is disclosed. The apparatus includes logic a plurality of execution units to execute single instruction, multiple data (SIMD) and flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels.

公开(公告)号：EP3382539A1

公开(公告)日：2018-10-03

申请号：EP18165314.8

申请日：2018-03-30

申请人： INTEL Corporation

发明人： KOKER, Altug ,  SURTI, Prasoonkumar ,  PUFFER, David ,  MAIYURAN, Subramaniam ,  LUEH, Guei-Yuan ,  APPU, Abhishek R. ,  RAY, Joydeep ,  VEMBU, Balaji ,  BAR-ON, Tomer ,  LAURITZEN, Andrew T. ,  LABBE, Hugues ,  GIERACH, John G. ,  LIKTOR, Gabor

IPC分类号： G06F9/46 ,  G06F9/48

CPC分类号： G06F17/30091 ,  G06F9/30 ,  G06F9/38 ,  G06F9/3836 ,  G06F9/461 ,  G06F9/48 ,  G06F17/30073 ,  G06F17/30132 ,  G06F2201/84

摘要： In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.