公开(公告)号：EP4336369A3

公开(公告)日：2024-06-19

申请号：EP24153968.3

申请日：2017-07-01

申请人： Intel Corporation

发明人： Valentine, Robert ,  Baum, Dan ,  Sperber, Zeev ,  Corbal, Jesus ,  Ould-Ahmed-Vall, ElMoustapha ,  Toll, Bret L. ,  Charney, Mark J. ,  Ziv, Barukh ,  Heinecke, Alexander ,  Girkar, Milind ,  Rubanovich, Simon

IPC分类号： G06F9/30 ,  G06F7/00 ,  G06F9/345 ,  G06F9/38

CPC分类号： G06F9/30036 ,  G06F2212/45520130101 ,  G06F12/0207 ,  G06F2212/45420130101 ,  G06F9/3001 ,  G06F7/5443 ,  G06F9/3861 ,  G06F9/30014 ,  G06F9/3016

摘要： Embodiments detailed herein relate to matrix operations. For example, in some embodiments, a processor comprises decode circuitry to decode an instruction having fields for an opcode, for identifying a first plurality of source vectors, for identifying a second plurality of source vectors, and for identifying a plurality of destination vectors; and execution circuitry to execute the decoded instruction to, for each data element position of each of the identified first plurality of source vectors: add a first data value at that data element position to a second data value at a corresponding data element position of a corresponding one of the identified second plurality of source vectors, and store a result of the addition into a corresponding data element position of a corresponding one of the identified plurality of destination vectors.

公开(公告)号：EP4354303A2

公开(公告)日：2024-04-17

申请号：EP24153964.2

申请日：2017-07-01

申请人： Intel Corporation

发明人： Valentine, Robert ,  Baum, Dan ,  Sperber, Zeev ,  Corbal, Jesus ,  Ould-Ahmed-Vall, ElMoustapha ,  Toll, Bret L. ,  Charney, Mark J. ,  Ziv, Barukh ,  Heinecke, Alexander ,  Girkar, Milind ,  Rubanovich, Simon

IPC分类号： G06F12/02

CPC分类号： G06F9/30036 ,  G06F2212/45520130101 ,  G06F12/0207 ,  G06F2212/45420130101 ,  G06F9/3001 ,  G06F7/5443 ,  G06F9/3861 ,  G06F9/30014 ,  G06F9/3016

摘要： Embodiments detailed herein relate to matrix operations. For example, in some embodiments, a processor comprises decode circuitry to decode an instruction having fields for an opcode, for identifying a first plurality of source vectors, for identifying a second plurality of source vectors, and for identifying a plurality of destination vectors; and execution circuitry to execute the decoded instruction to, for each data element position of each of the identified first plurality of source vectors: subtract, from a first data value at that data element position, a second data value at a corresponding data element position of a corresponding one of the identified second plurality of source vectors, and store a result of the subtraction into a corresponding data element position of a corresponding one of the identified plurality of destination vectors.

公开(公告)号：EP4336369A2

公开(公告)日：2024-03-13

申请号：EP24153968.3

申请日：2017-07-01

申请人： Intel Corporation

发明人： Valentine, Robert ,  Baum, Dan ,  Sperber, Zeev ,  Corbal, Jesus ,  Ould-Ahmed-Vall, ElMoustapha ,  Toll, Bret L. ,  Charney, Mark J. ,  Ziv, Barukh ,  Heinecke, Alexander ,  Girkar, Milind ,  Rubanovich, Simon

IPC分类号： G06F12/02

摘要： Embodiments detailed herein relate to matrix operations. For example, in some embodiments, a processor comprises decode circuitry to decode an instruction having fields for an opcode, for identifying a first plurality of source vectors, for identifying a second plurality of source vectors, and for identifying a plurality of destination vectors; and execution circuitry to execute the decoded instruction to, for each data element position of each of the identified first plurality of source vectors: add a first data value at that data element position to a second data value at a corresponding data element position of a corresponding one of the identified second plurality of source vectors, and store a result of the addition into a corresponding data element position of a corresponding one of the identified plurality of destination vectors.

公开(公告)号：EP4354303A3

公开(公告)日：2024-06-26

申请号：EP24153964.2

申请日：2017-07-01

申请人： Intel Corporation

发明人： Valentine, Robert ,  Baum, Dan ,  Sperber, Zeev ,  Corbal, Jesus ,  Ould-Ahmed-Vall, ElMoustapha ,  Toll, Bret L. ,  Charney, Mark J. ,  Ziv, Barukh ,  Heinecke, Alexander ,  Girkar, Milind ,  Rubanovich, Simon

IPC分类号： G06F9/30 ,  G06F7/00 ,  G06F9/345 ,  G06F9/38

CPC分类号： G06F9/30036 ,  G06F2212/45520130101 ,  G06F12/0207 ,  G06F2212/45420130101 ,  G06F9/3001 ,  G06F7/5443 ,  G06F9/3861 ,  G06F9/30014 ,  G06F9/3016

摘要： Embodiments detailed herein relate to matrix operations. For example, in some embodiments, a processor comprises decode circuitry to decode an instruction having fields for an opcode, for identifying a first plurality of source vectors, for identifying a second plurality of source vectors, and for identifying a plurality of destination vectors; and execution circuitry to execute the decoded instruction to, for each data element position of each of the identified first plurality of source vectors: subtract, from a first data value at that data element position, a second data value at a corresponding data element position of a corresponding one of the identified second plurality of source vectors, and store a result of the subtraction into a corresponding data element position of a corresponding one of the identified plurality of destination vectors.

公开(公告)号：EP4137941A1

公开(公告)日：2023-02-22

申请号：EP22196776.3

申请日：2017-07-01

申请人： Intel Corporation

发明人： Valentine, Robert ,  Baum, Dan ,  Sperber, Zeev ,  Corbal, Jesus ,  Ould-Ahmed-Vall, Elmoustapha ,  Toll, Bret L. ,  Charney, Mark J. ,  Ziv, Barukh ,  Heinecke, Alexander ,  Girkar, Milind ,  Rubanovich, Simon

IPC分类号： G06F9/30 ,  G06F7/544 ,  G06F9/345 ,  G06F9/38 ,  G06F12/02

摘要： Embodiments detailed herein relate to matrix operations. For example, in some embodiments, a processor comprises decode circuitry to decode an instruction having fields for an opcode, a first source matrix operand identifier, a second source matrix operand identifier, and a destination matrix operand identifier, wherein each of the first source matrix operand, the second source matrix operand, and the destination matrix operand corresponds to a two-dimensional matrix of values, and execution circuitry to execute the decoded instruction to, for each data element position of the identified first source matrix operand: multiply a first data value at that data element position by a second data value at a corresponding data element position of the identified second source matrix operand, and store a result of the multiplication into a corresponding data element position of the identified destination matrix operand.