公开(公告)号：EP4202656A1

公开(公告)日：2023-06-28

申请号：EP22206859.5

申请日：2022-11-11

申请人： INTEL Corporation

发明人： Ould-Ahmed-Vall, Elmoustapha

IPC分类号： G06F9/30

摘要： Techniques for prefetching random data and instructions using implicitly reference random number data are described. An example includes decode circuitry to decode a single instruction at least having a field for an opcode, the opcode to indicate execution circuitry is to perform an operation using implicitly referenced random data; and execution circuitry to execute the decoded single instruction according to the opcode.

公开(公告)号：EP2889756A1

公开(公告)日：2015-07-01

申请号：EP14194109.6

申请日：2014-11-20

申请人： Intel Corporation

发明人： Uliel, Tal ,  Ould-Ahmed-Vall, Elmoustapha ,  Valentine, Robert ,  Willhalm, Thomas

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/3013

摘要： Systems, methods, and apparatuses for vector bit test are described. In some embodiments, a vector bit test instruction is executed to shift each packed data element of a first source by a number of bits indicated by a corresponding packed data element of a second source, and store consecutive bit values from each packed data element of the first source at the identified bit positions of a corresponding packed data element of a destination.

摘要翻译： 描述用于向量比特测试的系统，方法和装置。 在一些实施例中，执行向量比特测试指令以将第一源的每个打包数据元素移位由第二源的对应的打包数据元素指示的位数，并且存储来自第二源的每个打包数据元素的连续位值 在目的地的相应的打包数据元素的所识别的位位置处的第一源。

公开(公告)号：EP4137940A1

公开(公告)日：2023-02-22

申请号：EP22196743.3

申请日：2017-07-01

申请人： Intel Corporation

发明人： Valentine, Robert ,  Sperber, Zeev ,  Charney, Mark J. ,  Toll, Bret L. ,  Rappoport, Rinat ,  Shwartsman, Stanislav ,  Baum, Dan ,  Yanover, Igor ,  Ould-Ahmed-Vall, Elmoustapha ,  Adelman, Menachem ,  Corbal, Jesus ,  Gebil, Yuri ,  Rubanovich, Simon

IPC分类号： G06F9/30 ,  G06F7/00 ,  G06F9/345 ,  G06F9/38

摘要： Embodiments detailed herein relate to matrix operations. For example, in some embodiments, a processor comprises decode circuitry to decode an instruction having fields for an opcode, an identifier for a first source matrix operand, an identifier of a second source matrix operand, and an identifier for a source/destination matrix operand, and execution circuitry to execute the decoded instruction to multiply the identified first source matrix operand by the identified second source matrix operand, add a result of the multiplication to the identified source/destination matrix operand, and store a result of the addition in the identified source/destination matrix operand.

公开(公告)号：EP4012555A1

公开(公告)日：2022-06-15

申请号：EP22154164.2

申请日：2017-07-01

申请人： Intel Corporation

发明人： Valentine, Robert ,  Baum, Dan ,  Sperber, Zeev ,  Corbal, Jesus ,  Ould-Ahmed-Vall, Elmoustapha ,  Toll, Bret L. ,  Charney, Mark J. ,  Adelman, Menachem ,  Ziv, Barukh ,  Heinecke, Alexander ,  Rubanovich, Simon

IPC分类号： G06F9/30

摘要： Embodiments detailed herein relate to matrix operations. For example, an apparatus comprises decode circuitry to decode an instruction and execution circuitry, coupled with the decode circuitry. The instruction has fields to indicate a first M row by K column (MxK) matrix, a second K row by N column (KxN) matrix, and a third M row by N column (MxN) matrix. The first MxK matrix has data elements of a first size, the second KxN matrix has data elements of the first size, and the third MxN matrix has data elements of a second size four times the first size. The execution circuitry performs operations corresponding to the instruction, including to: for each row of the first MxK matrix, and each column of the second KxN matrix: generate a dot-product from all data elements of the row of the first MxK matrix and all data elements of the column of the second KxN matrix, and accumulate the dot-product with a data element from a corresponding row and a corresponding column of the third MxN matrix.

公开(公告)号：EP2919112A2

公开(公告)日：2015-09-16

申请号：EP14195979.1

申请日：2014-12-02

申请人： Intel Corporation

发明人： Uliel, Tal ,  Ould-Ahmed-Vall, Elmoustapha ,  Valentine, Robert ,  Charney, Mark J. ,  Willhalm, Thomas

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036

摘要： A processor includes a decoder to receive an instruction that indicates first and second source packed data operands and at least one shift count. An execution unit is operable, in response to the instruction, to store a result packed data operand. Each result data element includes a first least significant bit (LSB) portion of a first data element of a corresponding pair of data elements in a most significant bit (MSB) portion, and a second MSB portion of a second data element of the corresponding pair in a LSB portion. One of the first LSB portion of the first data element and the second MSB portion of the second data element has a corresponding shift count number of bits. The other has a number of bits equal to a size of a data element of the first source packed data minus the corresponding shift count.

摘要翻译： 处理器包括解码器，用于接收指示第一和第二源压缩数据操作数和至少一个移位计数的指令。 执行单元响应于该指令可操作地存储结果打包数据操作数。 每个结果数据元素包括最高有效位（MSB）部分中对应的一对数据元素的第一数据元素的第一最低有效位（LSB）部分和相应对的第二数据元素的第二MSB部分 在LSB部分。 第一数据元素的第一LSB部分和第二数据元素的第二MSB部分之一具有相应的移位计数位数。 另一个具有等于第一源打包数据的数据元素的大小减去相应移位计数的位数。

公开(公告)号：EP4137941A1

公开(公告)日：2023-02-22

申请号：EP22196776.3

申请日：2017-07-01

申请人： Intel Corporation

发明人： Valentine, Robert ,  Baum, Dan ,  Sperber, Zeev ,  Corbal, Jesus ,  Ould-Ahmed-Vall, Elmoustapha ,  Toll, Bret L. ,  Charney, Mark J. ,  Ziv, Barukh ,  Heinecke, Alexander ,  Girkar, Milind ,  Rubanovich, Simon

IPC分类号： G06F9/30 ,  G06F7/544 ,  G06F9/345 ,  G06F9/38 ,  G06F12/02

摘要： Embodiments detailed herein relate to matrix operations. For example, in some embodiments, a processor comprises decode circuitry to decode an instruction having fields for an opcode, a first source matrix operand identifier, a second source matrix operand identifier, and a destination matrix operand identifier, wherein each of the first source matrix operand, the second source matrix operand, and the destination matrix operand corresponds to a two-dimensional matrix of values, and execution circuitry to execute the decoded instruction to, for each data element position of the identified first source matrix operand: multiply a first data value at that data element position by a second data value at a corresponding data element position of the identified second source matrix operand, and store a result of the multiplication into a corresponding data element position of the identified destination matrix operand.

公开(公告)号：EP3671439A1

公开(公告)日：2020-06-24

申请号：EP20155873.1

申请日：2018-03-23

申请人： Intel Corporation

发明人： Nealis, Kevin ,  Yao, Anbang ,  Chen, Xiaoming ,  Ould-Ahmed-Vall, Elmoustapha ,  Baghsorkhi, Sara S. ,  Nurvitadhi, Eriko ,  Vembu, Balaji ,  Galoppo von Borries, Nicolas C. ,  Barik, Rajkishore ,  Lin, Tsung-Han ,  Sinha, Kamal

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F7/523

摘要： One embodiment provides for a compute apparatus to perform machine learning operations, the apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including an input value and a quantized weight value associated with a neural network and an arithmetic logic unit including a barrel shifter, an adder, and an accumulator register, wherein to execute the decoded instruction, the barrel shifter is to shift the input value by the quantized weight value to generate a shifted input value and the adder is to add the shifted input value to a value stored in the accumulator register and update the value stored in the accumulator register.

公开(公告)号：EP2919112A3

公开(公告)日：2016-12-21

申请号：EP14195979.1

申请日：2014-12-02

申请人： Intel Corporation

发明人： Uliel, Tal ,  Ould-Ahmed-Vall, Elmoustapha ,  Valentine, Robert ,  Charney, Mark J. ,  Willhalm, Thomas

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036

摘要： A processor includes a decoder to receive an instruction that indicates first and second source packed data operands and at least one shift count. An execution unit is operable, in response to the instruction, to store a result packed data operand. Each result data element includes a first least significant bit (LSB) portion of a first data element of a corresponding pair of data elements in a most significant bit (MSB) portion, and a second MSB portion of a second data element of the corresponding pair in a LSB portion. One of the first LSB portion of the first data element and the second MSB portion of the second data element has a corresponding shift count number of bits. The other has a number of bits equal to a size of a data element of the first source packed data minus the corresponding shift count.