公开(公告)号：EP4180958A1

公开(公告)日：2023-05-17

申请号：EP22207277.9

申请日：2022-11-14

申请人： Intel Corporation

发明人： RAGHUNATH, Arun ,  CHOWDHURY, Mohammad ,  MESNIER, Michael P. ,  IYER, Ravishankar R. ,  ADAMS, Ian ,  METSCH, Thijs ,  BROWNE, John J. ,  HOBAN, Adrian ,  RAMAMURTHY, Veeraraghavan ,  KOEBERL, Patrick ,  GUIM BERNAT, Francesc ,  DOSHI, Kshitij Arun ,  BALLE, Susanne M. ,  LI, Bin

IPC分类号： G06F9/50

摘要： Various systems and methods for implementing computational storage are described herein. An orchestrator system is configured to: receive, at the orchestrator system, a registration package, the registration package including function code, a logical location of input data for the function code, and an event trigger for the function code, the event trigger set to trigger in response to when the input data is modified; interface with a storage service, the storage service to monitor the logical location of the input data and notify a location service when the input data is modified; interface with the location service to obtain a physical location of the input data, the location service to resolve the physical location from the logical location of the input data; and configure the function code to execute near the input data

公开(公告)号：EP3938882A1

公开(公告)日：2022-01-19

申请号：EP20769555.2

申请日：2020-03-12

申请人： Intel Corporation

发明人： MESNIER, Michael P. ,  KEYS, John S. ,  ADAMS, Ian F. ,  ZOU, Yi ,  MARIA REMIS, Luis Carlos ,  MCLERAN, Daniel Robert ,  BARCZAK, Mariusz ,  RAGHUNATH, Arun ,  KONG, Lay Wai

IPC分类号： G06F3/06

公开(公告)号：EP4064023A1

公开(公告)日：2022-09-28

申请号：EP22164358.8

申请日：2022-03-25

申请人： INTEL Corporation

发明人： ADAMS, Ian F. ,  MESNIER, Michael P. ,  AGRAWAL, Neha

IPC分类号： G06F3/06

摘要： In one embodiment, a device includes interface circuitry and processing circuitry. The interface circuitry communicates with a plurality of storage devices associated with a storage system. The processing circuitry receives a request to write a data object to the storage system. The data object includes a set of data elements, and the storage system is organized into blocks and shards, which are distributed across the storage devices. The processing circuitry determines a storage layout for the data object, which arranges the set of data elements across a set of blocks and shards with padding to align each data element within block and shard boundaries. The processing circuitry writes the data object to the storage system based on the storage layout.

公开(公告)号：EP3298752A1

公开(公告)日：2018-03-28

申请号：EP16796889.0

申请日：2016-04-14

申请人： Intel Corporation

发明人： WANG, Ren ,  ZHAO, Weishuang ,  MIN, Alexander W. ,  MESNIER, Michael P. ,  CHUANG, Richard ,  TAI, Tsung-Yuan C. ,  HAHN, Scott D.

IPC分类号： H04L29/06 ,  H04L29/08 ,  H04W84/02

CPC分类号： H04L47/38 ,  G06N5/003 ,  G06N7/005 ,  G06N99/005 ,  H03M7/30 ,  H04L43/0852 ,  H04L43/0894 ,  H04L47/20 ,  H04L67/306 ,  H04L69/04

摘要： Embodiments of apparatuses and methods for adaptive data compression and associated contextual information are described. In various embodiments, an apparatus may include a context monitoring module to gather contextual information for transmission of data and a policy module to gather user preference on cost associated with transmission of data. The apparatus may further include an analysis module to determine whether to compress data prior to transmission, based at least in part on the contextual information and the user preference. Other embodiments may be described and/or claimed.