公开(公告)号：EP2974024A1

公开(公告)日：2016-01-20

申请号：EP14770873.9

申请日：2014-02-25

申请人： Intel Corporation

发明人： HUANG, Choupin ,  BODDU, Vijaya K. ,  RUSU, Stefan ,  PETERSON, Nicholas B.

IPC分类号： H03K19/0175 ,  H03L7/07

CPC分类号： H03L7/07 ,  G06F1/06 ,  G06F1/10 ,  G06F3/167 ,  H03L7/08 ,  H03L7/0891 ,  H03L2207/06

摘要： A first phase locked loop (PLL) circuit having a first clocking ratio is coupled to receive an input differential clock signal and generates a first reference clock signal. A second PLL circuit having a second clocking ratio is coupled to receive the input differential clock signal and to generate a second reference clock signal. A first set of clock signal output buffers are coupled to receive the first reference clock signal and provide a first differential reference clock signal corresponding. A second set of clock signal output buffers is coupled to receive the second reference clock signal and provide a second differential reference clock signal. The first and second PLL circuits, and the first and second sets of output buffers reside within an integrated circuit package having a die to receive at least the first differential reference clock signal.

摘要翻译： 耦合具有第一时钟比率的第一锁相环（PLL）电路以接收输入差分时钟信号并产生第一参考时钟信号。 耦合具有第二时钟比的第二PLL电路以接收输入差分时钟信号并产生第二参考时钟信号。 耦合第一组时钟信号输出缓冲器以接收第一参考时钟信号并提供对应的第一差分参考时钟信号。 第二组时钟信号输出缓冲器被耦合以接收第二参考时钟信号并提供第二差分参考时钟信号。 第一和第二PLL电路以及第一和第二组输出缓冲器驻留在具有至少接收第一差分参考时钟信号的管芯的集成电路封装内。