公开(公告)号：EP1962426B1

公开(公告)日：2018-06-27

申请号：EP08157859.3

申请日：2002-08-23

申请人： Rambus Inc.

发明人： Chang, Kun-Yung, K. ,  Wei, Jason, C. ,  Perino, Donald, V.

IPC分类号： H03L7/085 ,  H04L7/02

CPC分类号： H03L7/0805 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/089 ,  H03L7/091 ,  H04L7/0004 ,  H04L7/0337 ,  H04L7/10

摘要： A clock data recovery (CDR) circuit to recover a clock signal and data signal from an input signal. The CDR circuit includes a control circuit; a select circuit and a phase adjust circuit. The control circuit generates a first control signal according to a phase relationship between the input signal and a first clock signal. The select circuit is coupled to receive the first control signal from the control circuit and coupled to receive a second control signal. The select circuit is responsive to a select signal to select either the first control signal or the second control signal to be output as a selected control signal. The phase adjust circuit is coupled to receive the selected control signal from the select circuit, the phase adjust circuit being responsive to the selected control signal to adjust the phase of the first clock signal.

公开(公告)号：EP2599226B1

公开(公告)日：2018-06-20

申请号：EP11813056.6

申请日：2011-07-26

申请人： Marvell World Trade Ltd.

发明人： ROMANO, Luca ,  VENCA, Alessandro ,  DAL TOSO, Stefano ,  MILANI, Antonio ,  BRUNN, Brian

IPC分类号： H03L7/16

CPC分类号： H03L7/08 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0816 ,  H03L7/16 ,  H03L7/1976

摘要： In one embodiment, an apparatus includes a jitter generator configured to receive a reference clock; add jitter to the reference clock; and output the reference clock with the included jitter to a phase lock loop (PLL). The PLL is used to generate a local oscillator (LO) signal for a transceiver. A jitter controller outputs a signal to the jitter generator to control a characteristic of the jitter added to the reference clock. The reference clock with the added jitter is used to reduce a fractional spur caused by a radio frequency (RF) attacker coupling into the PLL.

公开(公告)号：EP3311493A2

公开(公告)日：2018-04-25

申请号：EP16757973.9

申请日：2016-08-09

申请人： Josefsberg, Yekutiel ,  Lavian, Tal I.

发明人： Josefsberg, Yekutiel ,  Lavian, Tal I.

IPC分类号： H03L7/185 ,  H03L7/20 ,  H03L7/113 ,  H03L7/085

CPC分类号： H03L7/085 ,  H03L1/028 ,  H03L7/07 ,  H03L7/099 ,  H03L7/113 ,  H03L7/185 ,  H03L7/20 ,  H03L7/23 ,  H03L7/24

摘要： A system for providing ultra low phase noise frequency synthesizers using Fractional-N PLL (Phase Lock Loop), Sampling Reference PLL and DDS (Direct Digital Synthesizer). Modern day advanced communication systems comprise frequency synthesizers that provide a frequency output signal to other parts of the transmitter and receiver so as to enable the system to operate at the set frequency band. The performance of the frequency synthesizer determines the performance of the communication link. Current days advanced communication systems comprises single loop Frequency synthesizers which are not completely able to provide lower phase deviations for errors (For 256 QAM the practical phase deviation for no errors is 0.4-0.5°) which would enable users to receive high data rate. This proposed system overcomes deficiencies of current generation state of the art communication systems by providing much lower level of phase deviation error which would result in much higher modulation schemes and high data rate.

公开(公告)号：EP3100357A4

公开(公告)日：2017-10-11

申请号：EP15744089

申请日：2015-01-14

申请人： MICROSEMI SEMICONDUCTOR ULC

发明人： MILIJEVIC SLOBODAN

IPC分类号： H03L7/07 ,  H03L7/099 ,  H04L7/00

CPC分类号： H03L7/087 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0807 ,  H03L7/0991 ,  H03L7/22

摘要： A double phase-locked has a first phase-locked loop including a first narrowband loop filter configured to reduce phase noise in a first input clock, and a second phase-locked loop including a second loop filter configured to receive a second input clock from a stable clock source. The second clock has a frequency close to said first clock. The first loop has a bandwidth at least an order of magnitude less than the second loop. A coupler couples the first and second phase-locked loops to provide a common output. The double phase-locked loop can be used, for example, to provide time-of-day information in wireless networks or as a fine filter for cleaning phase noise from clock signals recovered over telecom/datacom networks.

公开(公告)号：EP3217555A1

公开(公告)日：2017-09-13

申请号：EP16158953.6

申请日：2016-03-07

申请人： NXP B.V.

发明人： Leong, Frank ,  Janssen, Erwin

IPC分类号： H03L7/07 ,  H03L7/08 ,  H03L7/099 ,  H03L7/22

CPC分类号： H03M1/66 ,  H03L7/07 ,  H03L7/0807 ,  H03L7/099 ,  H03L7/22

摘要： A data conversion system and method are described. A first phase locked loop includes a controllable frequency oscillator circuit to receive a digital data stream and output a reference frequency signal, and includes an oscillator and at least one variable load connected to the oscillator which is controllable to tune the oscillator frequency and vary the frequency of the reference frequency signal. A second phase locked loop includes a divide by N function in a feedback loop (where N has an integer value), and receives the reference frequency signal and outputs a recovered clock signal corresponding to an oiiginal clock signal associated with the digital data stream. The recovered clock signal is used to clock a data converter to convert the digital data into an analog output signal.

摘要翻译： 描述了一种数据转换系统和方法。 第一锁相环包括可控频率振荡器电路，用于接收数字数据流并输出参考频率信号，并且包括振荡器和连接到该振荡器的至少一个可变负载，该可变负载可控制以调谐振荡器频率并改变频率 的参考频率信号。 第二锁相环在反馈回路（其中N具有整数值）中包括除N函数，并且接收参考频率信号并输出​​对应于与数字数据流相关联的最高时钟信号的恢复时钟信号。 恢复的时钟信号用于为数据转换器提供时钟，将数字数据转换为模拟输出信号。

公开(公告)号：EP2974024A4

公开(公告)日：2016-11-02

申请号：EP14770873

申请日：2014-02-25

申请人： INTEL CORP

发明人： HUANG CHOUPIN ,  BODDU VIJAYA K ,  RUSU STEFAN ,  PETERSON NICHOLAS B

IPC分类号： G06F1/04 ,  H03K19/0175 ,  H03L7/07 ,  H03L7/08

CPC分类号： H03L7/07 ,  G06F1/06 ,  G06F1/10 ,  G06F3/167 ,  H03L7/08 ,  H03L7/0891 ,  H03L2207/06

公开(公告)号：EP3041136A1

公开(公告)日：2016-07-06

申请号：EP15200633.4

申请日：2015-12-17

申请人： Semtech Corporation

发明人： Shivaram, Krishna ,  Vandel, Eric

IPC分类号： H03K5/135 ,  H04L7/033 ,  H03L7/081 ,  H03L7/087 ,  H03L7/089 ,  H03L7/091 ,  H03L7/07 ,  H03L7/10 ,  G06F1/04

CPC分类号： H03L7/00 ,  G06F1/04 ,  G06F1/10 ,  H03K5/135 ,  H03K2005/00019 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/089 ,  H03L7/091 ,  H03L7/10

摘要： A clock synchronization circuit (fig. 4a) has a clock sync detector (fig. 4a: 182). A first variable delay circuit (fig. 4a: 172) is coupled to a first input (178) of the clock sync detector. A controller (fig. 4a: 184) is coupled to a digital output (208) of the clock sync detector and a control input (fig. 4a: 185) of the first variable delay circuit (fig. 4a: 172). A first clock signal (178) is coupled to the first variable delay circuit (fig. 4a: 172). A second clock signal (179) is coupled to a second input of the clock sync detector (179). The clock sync detector includes a first flip-flop (fig. 4c: 220, 222) and a first delay element (fig. 4c: 224, 226; 234, 236) coupled between the first variable delay circuit (fig. 4a: 172) and a data input of the first flip-flop (fig. 4c: 220). A second variable delay circuit (fig. 4a: 174) is coupled to a second input (179) of the clock sync detector. A multiplexer (190, 192) is coupled between the first variable delay circuit (fig. 4a: 172) and the first input (178) of the clock sync detector. An offset compensation (201) calibrates (signal 202) the clock sync detector.

摘要翻译： 一种时钟同步电路（图4A）具有时钟同步检测器（图4a：182）。 第一可变延迟电路（图4A：172）被耦合到所述时钟同步检测器的第一输入端（178）。 控制器（图4A：184）被耦合到所述时钟同步检测器的数字输出（208）和一个控制输入端：（：172图4a）所述第一可变延迟电路的（图4a中185）。 第一时钟信号（178）被耦合到所述第一可变延迟电路（图4a：172）。 第二时钟信号（179）被耦合到所述时钟同步检测器（179）的第二输入端。 时钟同步检测器包括：第一触发器（图4C：220,222）和第一延迟元件（图4C：224,226; 234，236 ,.）耦合在所述第一可变延迟电路（图4a 172之间。 ）和所述第一触发器的一个数据输入端（图4C：220）。 第二可变延迟电路（图4a：174）被耦合到所述时钟同步检测器的第二输入端（179）。 复用器（190，192）被耦合在所述第一可变延迟电路之间（图4a：172）和时钟同步检测器的第一输入端（178）。 校正到偏移补偿（201）（信号202）中的时钟同步检测器。

公开(公告)号：EP2860873B1

公开(公告)日：2016-06-15

申请号：EP14187063.4

申请日：2014-09-30

申请人： Thomas & Betts International, LLC

发明人： Walraven, Justin

IPC分类号： H03L7/07 ,  H02J9/06

CPC分类号： H03L7/0805 ,  H02J9/062 ,  H02J2009/068 ,  H03L7/07 ,  H03L7/095 ,  H03L2207/14

公开(公告)号：EP3002878A1

公开(公告)日：2016-04-06

申请号：EP15185700.0

申请日：2004-10-20

申请人： ROBERT BOSCH GMBH

发明人： Lutz, Markus ,  Partridge, Aaron

IPC分类号： H03L7/00 ,  H03B5/04 ,  H03B5/30 ,  H03L1/04 ,  H03L7/07 ,  H03L1/02 ,  H03L7/08 ,  H03L7/081 ,  H03L7/197

CPC分类号： H03L1/022 ,  H03B5/04 ,  H03B5/30 ,  H03L1/026 ,  H03L1/027 ,  H03L1/04 ,  H03L7/07 ,  H03L7/08 ,  H03L7/0812 ,  H03L7/1974

摘要： A compensated microelectromechanical oscillator, having a microelectromechanical resonator that generates an output signal and frequency adjustment circuitry, coupled to the microelectromechanical resonator to receive the output signal of the microelectromechanical resonator and, in response to a set of values, to generate an output signal having second frequency. In one embodiment, the values may be determined using the frequency of the output signal of the microelectromechanical resonator, which depends on the operating temperature of the microelectromechanical resonator and/or manufacturing variations of the microelectromechanical resonator. In one embodiment, the frequency adjustment circuitry may include frequency multiplier circuitry, for example, PLLs, DLLs, digital/frequency synthesizers and/or FLLs, as well as any combinations and permutations thereof. The frequency adjustment circuitry, in addition or in lieu thereof, may include frequency divider circuitry, for example, DLLs, digital/frequency synthesizers (for example, DDS) and/or FLLs, as well as any combinations and permutations thereof.

摘要翻译： 一种经补偿的微机电振荡器，其具有微机电谐振器，其产生输出信号和频率调节电路，耦合到微机电谐振器以接收微机电谐振器的输出信号，并且响应于一组值，以产生具有第二 频率。 在一个实施例中，可以使用取决于微机电谐振器的操作温度和/或微机电谐振器的制造变化的微机电谐振器的输出信号的频率来确定值。 在一个实施例中，频率调整电路可以包括倍频器电路，例如PLL，DLL，数字/频率合成器和/或FLL，以及它们的任何组合和排列。 频率调节电路，除了或代替它，可以包括分频器电路，例如DLL，数字/频率合成器（例如，DDS）和/或FLL，以及它们的任何组合和排列。

公开(公告)号：EP2974024A1

公开(公告)日：2016-01-20

申请号：EP14770873.9

申请日：2014-02-25

申请人： Intel Corporation

发明人： HUANG, Choupin ,  BODDU, Vijaya K. ,  RUSU, Stefan ,  PETERSON, Nicholas B.

IPC分类号： H03K19/0175 ,  H03L7/07

CPC分类号： H03L7/07 ,  G06F1/06 ,  G06F1/10 ,  G06F3/167 ,  H03L7/08 ,  H03L7/0891 ,  H03L2207/06

摘要： A first phase locked loop (PLL) circuit having a first clocking ratio is coupled to receive an input differential clock signal and generates a first reference clock signal. A second PLL circuit having a second clocking ratio is coupled to receive the input differential clock signal and to generate a second reference clock signal. A first set of clock signal output buffers are coupled to receive the first reference clock signal and provide a first differential reference clock signal corresponding. A second set of clock signal output buffers is coupled to receive the second reference clock signal and provide a second differential reference clock signal. The first and second PLL circuits, and the first and second sets of output buffers reside within an integrated circuit package having a die to receive at least the first differential reference clock signal.

摘要翻译： 耦合具有第一时钟比率的第一锁相环（PLL）电路以接收输入差分时钟信号并产生第一参考时钟信号。 耦合具有第二时钟比的第二PLL电路以接收输入差分时钟信号并产生第二参考时钟信号。 耦合第一组时钟信号输出缓冲器以接收第一参考时钟信号并提供对应的第一差分参考时钟信号。 第二组时钟信号输出缓冲器被耦合以接收第二参考时钟信号并提供第二差分参考时钟信号。 第一和第二PLL电路以及第一和第二组输出缓冲器驻留在具有至少接收第一差分参考时钟信号的管芯的集成电路封装内。