公开(公告)号：EP4293503A1

公开(公告)日：2023-12-20

申请号：EP23171339.7

申请日：2023-05-03

Applicant: Intel Corporation

Inventor： Adelman, Menachem ,  Gradstein, Amit ,  Rubanovich, Simon ,  Ziv, Barukh ,  Sherman, Uri ,  Rip, Dana ,  Mizrahi, Shahar ,  Baum, Dan ,  Rappoport, Rinat ,  Jain, Nilesh ,  Sperber, Zeev ,  Stupp, Gideon ,  Heinecke, Alexander ,  Hughes, Christopher ,  Georganas, Evangelos

IPC: G06F9/30

Abstract: Techniques and mechanisms for processor circuitry to execute a load and expand instruction of an instruction set to generate decompressed matrix data. In an embodiment, the instruction comprises a source operand which indicates a location from which compressed matrix data, and corresponding metadata, are to be accessed. A destination operand of the instruction indicates a location which is to receive decompressed metadata, which is generated, during execution of the instruction, based on the compressed matrix data and the corresponding metadata. The metadata comprises compression mask information which identifies which elements of the matrix have been masked from the compressed matrix data. In another embodiment, the instruction further comprises a count operand which identifies a total number of the unmasked matrix elements which are represented in the compressed matrix data.

公开(公告)号：EP4216057A1

公开(公告)日：2023-07-26

申请号：EP23161367.0

申请日：2017-07-01

Applicant: INTEL Corporation

Inventor： Valentine, Robert ,  Sperber, Zeev ,  Charney, Mark J. ,  Toll, Bret L. ,  Rappoport, Rinat ,  Shwartsman, Stanislav ,  Baum, Dan ,  Yanover, Igor ,  Ould-Ahmed-Vall, ElMoustapha ,  Adelman, Menachem ,  Corbal, Jesus ,  Gebil, Yuri ,  Rubanovich, Simon

IPC: G06F9/30

Abstract: Embodiments detailed herein relate to matrix operations. For example, in some embodiments, an apparatus comprises an instruction decoder to decode a single instruction, the single instruction having fields to indicate an opcode, a first register to store a first source matrix, a second register to store a second source matrix, and a third register to store a 2 by 2 third source matrix, wherein the opcode is to indicate a matrix multiply-accumulate operation; and execution circuitry to perform the matrix multiply-accumulate operation. The matrix multiply-accumulate operation includes: multiplying a value corresponding to a first row and a first column of the first source matrix and a value corresponding to a first row and a first column of the second source matrix to generate a first product, multiplying a value corresponding to the first row and a second column of the first source matrix and a value corresponding to a second row and the first column of the second source matrix to generate a second product, summing the first product, the second product, and an initial value corresponding to an element position in a first row and a first column of the 2 by 2 third source matrix to generate a resulting value corresponding to the element position in a destination matrix, and storing the destination matrix in the third register.

公开(公告)号：EP4137940A1

公开(公告)日：2023-02-22

申请号：EP22196743.3

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Valentine, Robert ,  Sperber, Zeev ,  Charney, Mark J. ,  Toll, Bret L. ,  Rappoport, Rinat ,  Shwartsman, Stanislav ,  Baum, Dan ,  Yanover, Igor ,  Ould-Ahmed-Vall, Elmoustapha ,  Adelman, Menachem ,  Corbal, Jesus ,  Gebil, Yuri ,  Rubanovich, Simon

IPC: G06F9/30 ,  G06F7/00 ,  G06F9/345 ,  G06F9/38

Abstract: Embodiments detailed herein relate to matrix operations. For example, in some embodiments, a processor comprises decode circuitry to decode an instruction having fields for an opcode, an identifier for a first source matrix operand, an identifier of a second source matrix operand, and an identifier for a source/destination matrix operand, and execution circuitry to execute the decoded instruction to multiply the identified first source matrix operand by the identified second source matrix operand, add a result of the multiplication to the identified source/destination matrix operand, and store a result of the addition in the identified source/destination matrix operand.