公开(公告)号：EP4016599A1

公开(公告)日：2022-06-22

申请号：EP21195724.6

申请日：2021-09-09

申请人： Intel Corporation

发明人： Wei, Andy ,  Park, Changyok ,  Bouche, Guillaume ,  Ryu, Hyuk ,  Wallace, Charles ,  Haran, Mohit

IPC分类号： H01L21/768

摘要： Disclosed herein are transistor arrangements with trench contacts that have two parts - a first trench contact and a second trench contact - stacked over one another. Such transistor arrangements may be fabricated by forming a first trench contact over a source or drain contact of a transistor, recessing the first trench contact, forming the second trench contact over the first trench contact, and, finally, forming a gate contact that is electrically isolated from, while being self-aligned to, the second trench contact. Such a fabrication process may provide improvements in terms of increased edge placement error margin, cost-efficiency, and device performance, compared to conventional approaches to forming trench and gate contacts. The conductive material of the first trench contact may also be deposited over the gate electrodes of transistors, forming a gate strap, to advantageously reduce gate resistance.