公开(公告)号：EP4138117A1

公开(公告)日：2023-02-22

申请号：EP22182715.7

申请日：2022-07-04

申请人： Intel Corporation

发明人： Wei, Andy ,  Bouche, Guillaume

IPC分类号： H01L21/336 ,  H01L29/775 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/528 ,  H01L23/535 ,  H01L29/78 ,  H01L29/16 ,  B82Y10/00

摘要： Techniques are provided to form semiconductor devices having a multi-layer spacer structure. In an example, a semiconductor device includes a semiconductor region extending between a source region and a drain region, and a gate layer extending over the semiconductor region. A spacer structure made up of one or more dielectric layers is present along a sidewall of the gate structure and along a sidewall of the source region or the drain region. The spacer structure has three different portions: a first portion along the sidewall of the gate, a second portion along the sidewall of the source or drain region, and a third portion that connects between the first two portions. The third portion of the spacer structure has a multi-layer configuration while the first and second portions have a fewer number of material layers.

公开(公告)号：EP4016599A1

公开(公告)日：2022-06-22

申请号：EP21195724.6

申请日：2021-09-09

申请人： Intel Corporation

发明人： Wei, Andy ,  Park, Changyok ,  Bouche, Guillaume ,  Ryu, Hyuk ,  Wallace, Charles ,  Haran, Mohit

IPC分类号： H01L21/768

摘要： Disclosed herein are transistor arrangements with trench contacts that have two parts - a first trench contact and a second trench contact - stacked over one another. Such transistor arrangements may be fabricated by forming a first trench contact over a source or drain contact of a transistor, recessing the first trench contact, forming the second trench contact over the first trench contact, and, finally, forming a gate contact that is electrically isolated from, while being self-aligned to, the second trench contact. Such a fabrication process may provide improvements in terms of increased edge placement error margin, cost-efficiency, and device performance, compared to conventional approaches to forming trench and gate contacts. The conductive material of the first trench contact may also be deposited over the gate electrodes of transistors, forming a gate strap, to advantageously reduce gate resistance.

公开(公告)号：EP4125117A1

公开(公告)日：2023-02-01

申请号：EP22159400.5

申请日：2022-03-01

申请人： Intel Corporation

发明人： Wei, Andy ,  Cheng, Yang-Chun ,  Chowdhury, Shaestagir ,  Bouche, Guillaume

IPC分类号： H01L21/74 ,  H01L21/768 ,  H01L23/528 ,  H01L23/535 ,  H01L21/8238

摘要： Techniques to form self-aligned lateral contacts. In an example, a first trench contact contacts a source or drain region of a transistor. A second trench contact includes non-contiguous first and second portions, each portion having a top surface that is co-planar with a top surface of the first trench contact as well as a top surface of the gate structure. A sidewall of the second trench contact is self-aligned to, and interfaces with, a sidewall of the first trench contact. A via extends from the first portion of the second trench contact to an underlying power rail. In some cases, the second portion of the second trench contact extends over a source or drain region of another transistor, without contacting that source or drain region. The fly-over portion of the second trench contact has a maximum height that is shorter than a maximum height of the first trench contact.

公开(公告)号：EP3886176A1

公开(公告)日：2021-09-29

申请号：EP20207504.0

申请日：2020-11-13

申请人： INTEL Corporation

发明人： Bouche, Guillaume ,  Wei, Andy Chih-Hung ,  Ma, Sean T.

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/417

摘要： Discussed herein is device contact sizing in integrated circuit (IC) structures. In some embodiments, an IC structure may include: a first source/drain (S/D) contact (164-1) in contact with a first S/D region (128), and a second S/D contact (164-2) in contact with a second S/D region (130), wherein the first S/D region (128) and the second S/D region (130) have a same length, and the first S/D contact (164-1) and the second S/D contact (164-2) have different lengths (252-1, 252-2).

公开(公告)号：EP3993062A1

公开(公告)日：2022-05-04

申请号：EP21190793.6

申请日：2021-08-11

申请人： Intel Corporation

发明人： Wei, Andy Chih-Hung ,  Murthy, Anand S. ,  Kobrinsky, Mauro J. ,  Bouche, Guillaume

IPC分类号： H01L29/775 ,  H01L29/06 ,  H01L21/336 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/40 ,  B82Y10/00

摘要： Methods for fabricating a transistor arrangement of an IC structure by using a placeholder for backside contact formation, as well as related semiconductor devices, are disclosed. An example method includes forming, in a support structure (e.g., a substrate, a chip, or a wafer), a dielectric placeholder for a backside contact as the first step in the method. A nanosheet superlattice is then grown laterally over the dielectric placeholder, and a stack of nanoribbons is formed based on the superlattice. The nanoribbons are processed to form S/D regions and gate stacks for future transistors. The dielectric placeholder remains in place until the support structure is transferred to a carrier wafer, at which point the dielectric placeholder is replaced with the backside contact. Use of a placeholder for backside contact formation allows alignment of contact from the backside to appropriate device ports of a transistor arrangement.

公开(公告)号：EP4057327A1

公开(公告)日：2022-09-14

申请号：EP22150660.3

申请日：2022-01-10

申请人： Intel Corporation

发明人： Wei, Andy Chih-Hung ,  Bouche, Guillaume

IPC分类号： H01L21/768 ,  H01L23/522

摘要： Disclosed herein are methods for fabricating IC structures that include stacked vias providing electrical connectivity between metal lines of different layers of a metallization stack, as well as resulting IC structures. An example IC structure includes a first and a second metallization layers, including, respectively, a bottom metal line and a top metal line. The IC structure further includes a via that has a bottom via portion and a top via portion, where the top via portion is stacked over the bottom via portion (hence, the via may be referred to as a "stacked via"). The bottom via portion is coupled and self-aligned to the bottom electrically conductive line, while the top via portion is coupled and self-aligned to the top electrically conductive line. The bottom via portion is formed using selective growth, e.g., assisted by a self-assembled monolayer (SAM) material.