公开(公告)号：EP3948531A1

公开(公告)日：2022-02-09

申请号：EP19921047.7

申请日：2019-03-28

申请人： INTEL Corporation

发明人： TIAN, Kun ,  ZHAO, Yan ,  ZHANG, Yu

IPC分类号： G06F9/455

公开(公告)号：EP3483932A2

公开(公告)日：2019-05-15

申请号：EP18214233.1

申请日：2015-12-03

申请人： INTEL Corporation

发明人： QIAN, Zhiguo ,  AYGUN, Kemal ,  ZHANG, Yu

IPC分类号： H01L23/498

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

公开(公告)号：EP3234993A1

公开(公告)日：2017-10-25

申请号：EP15870674.7

申请日：2015-12-03

申请人： Intel Corporation

发明人： QIAN, Zhiguo ,  AYGUN, Kemal ,  ZHANG, Yu

IPC分类号： H01L23/48

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例针对用于集成电路（IC）组件中的串扰抑制的接地通孔集群的技术和配置。 在一些实施例中，IC封装组件可以包括被配置为在管芯和第二封装衬底之间路由输入/输出（I / O）信号和接地的第一封装衬底。 第一封装衬底可以包括设置在第一封装衬底的一侧上的多个触点和同一层通路的至少两个接地过孔，并且至少两个接地过孔可以形成与一个电连接到 个人联系。 其他实施例可以被描述和/或要求保护。

公开(公告)号：EP4220709A3

公开(公告)日：2023-08-09

申请号：EP22217374.2

申请日：2015-12-03

申请人： INTEL Corporation

发明人： QIAN, Zhiguo ,  AYGUN, Kemal ,  ZHANG, Yu

IPC分类号： H01L23/498

摘要： The present disclosure relates to a method of making a semiconductor package, a computing device including a package substrate and a semiconductor package, comprising a package substrate having a first side and a second side opposite the first side, the package substrate comprising: a first layer of dielectric material adjacent the first side of the package substrate; a second layer of dielectric material on the first layer of dielectric material, the first layer of dielectric material being between the second layer of dielectric material and the first side of the package substrate; a ground solder ball pad adjacent the first side of the package substrate; a first via above and electrically coupled to the ground solder ball pad, the first via being in the first layer of dielectric material of the package substrate; a second via above and electrically coupled to the ground solder ball pad, the second via being in the first layer of dielectric material of the package substrate, the second via laterally spaced apart from the first via; a third via above and electrically coupled to the first via and being in the second layer of dielectric material of the package substrate; a fourth via above and electrically coupled to the second via and being in the second layer of dielectric material of the package substrate, the fourth via laterally spaced apart from the third via; wherein a first line perpendicular to the first side of the package substrate intersects the ground solder ball pad, the first via, and the third via; and wherein a second line perpendicular to the first side of the package substrate intersects the ground solder ball pad, the second via, and the fourth via; a die coupled to the second side of the package substrate; and a solder ball disposed on the ground solder ball pad.

公开(公告)号：EP3799118A3

公开(公告)日：2021-10-06

申请号：EP20200804.1

申请日：2015-12-03

申请人： INTEL Corporation

发明人： QIAN, Zhiguo ,  AYGUN, Kemal ,  ZHANG, Yu

IPC分类号： H01L23/498

摘要： Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

公开(公告)号：EP4220709A2

公开(公告)日：2023-08-02

申请号：EP22217374.2

申请日：2015-12-03

申请人： INTEL Corporation

发明人： QIAN, Zhiguo ,  AYGUN, Kemal ,  ZHANG, Yu

IPC分类号： H01L23/498

摘要： The present disclosure relates to a method of making a semiconductor package, a computing device including a package substrate and a semiconductor package, comprising a package substrate having a first side and a second side opposite the first side, the package substrate comprising: a first layer of dielectric material adjacent the first side of the package substrate; a second layer of dielectric material on the first layer of dielectric material, the first layer of dielectric material being between the second layer of dielectric material and the first side of the package substrate; a ground solder ball pad adjacent the first side of the package substrate; a first via above and electrically coupled to the ground solder ball pad, the first via being in the first layer of dielectric material of the package substrate; a second via above and electrically coupled to the ground solder ball pad, the second via being in the first layer of dielectric material of the package substrate, the second via laterally spaced apart from the first via; a third via above and electrically coupled to the first via and being in the second layer of dielectric material of the package substrate; a fourth via above and electrically coupled to the second via and being in the second layer of dielectric material of the package substrate, the fourth via laterally spaced apart from the third via; wherein a first line perpendicular to the first side of the package substrate intersects the ground solder ball pad, the first via, and the third via; and wherein a second line perpendicular to the first side of the package substrate intersects the ground solder ball pad, the second via, and the fourth via; a die coupled to the second side of the package substrate; and a solder ball disposed on the ground solder ball pad.

公开(公告)号：EP3951867A1

公开(公告)日：2022-02-09

申请号：EP21175747.1

申请日：2015-12-03

申请人： INTEL Corporation

发明人： QIAN, Zhiguo ,  AYGUN, Kemal ,  ZHANG, Yu

IPC分类号： H01L23/498

摘要： The present disclosure provides a semiconductor package, comprising a package substrate having a first side and a second side, the first side opposite the second side. The package substrate comprising a layer comprising a semiconductor material, a plurality of contacts disposed on the second side of the package substrate, a cluster of ground vias with at least two ground vias of a same layer to electrically couple with an individual contact of the plurality of contacts, six signal vias surrounding the cluster of ground vias in a hexagonal arrangement and a die coupled to the first side of the package substrate.

公开(公告)号：EP3847590A1

公开(公告)日：2021-07-14

申请号：EP18932401.5

申请日：2018-09-07

申请人： Intel Corporation

发明人： ZHANG, Yu ,  LE, Huifeng ,  CHUANG, Richard ,  WERNER, Metz, Jr. ,  HAN, Heng Juen ,  ZHANG, Ning ,  SHAO, Wenjian ,  HE, Ke

IPC分类号： G06N3/063

公开(公告)号：EP3799118A2

公开(公告)日：2021-03-31

申请号：EP20200804.1

申请日：2015-12-03

申请人： INTEL Corporation

发明人： QIAN, Zhiguo ,  AYGUN, Kemal ,  ZHANG, Yu

IPC分类号： H01L23/498

摘要： Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

公开(公告)号：EP3483932A3

公开(公告)日：2019-08-28

申请号：EP18214233.1

申请日：2015-12-03

申请人： INTEL Corporation

发明人： QIAN, Zhiguo ,  AYGUN, Kemal ,  ZHANG, Yu

IPC分类号： H01L23/498

摘要： Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.