公开(公告)号：EP2761468A1

公开(公告)日：2014-08-06

申请号：EP11873492.0

申请日：2011-09-30

申请人： Intel Corporation

发明人： ZIMMER, Vincent, J. ,  ROTHMAN, Michael, A. ,  DORAN, Mark, S.

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F9/4401 ,  G06F12/0238 ,  G06F12/0638 ,  G06F12/0653 ,  G06F2212/1016 ,  G06F2212/1041 ,  G06F2212/2024 ,  G06F2212/214 ,  Y02D10/13

摘要： A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in a platform storage hierarchy. The NVRAM is byte-addressable by the processor and can be configured into one or more partitions, with each partition implementing a different tier of the platform storage hierarchy. The NVRAM can be used as mass storage that can be accessed without a storage driver.

公开(公告)号：EP1964020A1

公开(公告)日：2008-09-03

申请号：EP06845166.5

申请日：2006-12-06

申请人： Intel Corporation

发明人： NEMIROFF, Daniel ,  HERBERT, Howard, C. ,  DIAMANT, Nimrod ,  MAOR, Moshe ,  SMITH, Carey, W. ,  HUFFMAN, Amber ,  CORRADO, Fran ,  ROTHMAN, Michael, A. ,  ZIMMER, Vincent, J.

IPC分类号： G06F21/02

CPC分类号： G06F21/805

摘要： A computer system is disclosed. The computer system includes a storage device/ a device controller and a chipset. The device controller includes lock registers having values that correspond to the ranges of locked sectors of the storage device. The lock registers verify if a storage device access request is targeted for ranges of sectors of the storage device that are locked. The chipset includes an embedded controller to authenticate the storage device access request and to manage configuration of the storage device.

公开(公告)号：EP2761468B1

公开(公告)日：2019-12-11

申请号：EP11873492.0

申请日：2011-09-30

申请人： Intel Corporation

发明人： ZIMMER, Vincent, J. ,  ROTHMAN, Michael, A. ,  DORAN, Mark, S.

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F9/44 ,  G06F12/06 ,  G06F9/4401

公开(公告)号：EP3271818A1

公开(公告)日：2018-01-24

申请号：EP16765391.4

申请日：2016-02-18

申请人： Intel Corporation

发明人： KOTARY, Karunakara ,  ZIMMER, Vincent, J. ,  BRENDEN, Scott, D. ,  BENCHIMOL, Jose ,  KUMAR, Panner ,  POORNACHANDRAN, Rajesh

IPC分类号： G06F9/445 ,  G06F9/44 ,  G06F21/57 ,  G06F11/20

CPC分类号： G06F21/575 ,  G06F21/74

摘要： A dynamic firmware module loader loads one of a plurality of a firmware contexts or modules as needed in a containerized environment for secure isolated execution. The modules, called applets, may be loaded and unloaded in a firmware context. The loader may use a hardware inter process communication channel (IPC) to communicate with the secure engine. The modules may be designed to implement specific features desired by basic input/output system vendors, without the use of a system management mode. Designed modules may provide necessary storage and I/O access driver capabilities to be run in trusted execution environment containers.

公开(公告)号：EP2656201A1

公开(公告)日：2013-10-30

申请号：EP11851655.8

申请日：2011-11-16

申请人： Intel Corporation

发明人： ROTHMAN, Michael, A. ,  SAKTHIKUMAR, Palsamy ,  ZIMMER, Vincent, J. ,  BULUSU, Mallik ,  SWANSON, Robert, C.

IPC分类号： G06F9/06 ,  G06F13/14 ,  G06F12/00

CPC分类号： G06F9/4418

摘要： A method and apparatus for improving the resume time of a platform. In one embodiment of the invention, the context of the platform is saved prior to entering an inactive state of the platform. When the platform is switched back to an active state, it reads the saved context and restores the platform to its original state prior to entering the inactive state. In one embodiment of the invention, the platform determines whether it should compress the saved context before storing it in a non-volatile memory based on the operating condition of the platform. This allows the platform to select the optimum method to allow faster resume time of the platform.

公开(公告)号：EP2619679A2

公开(公告)日：2013-07-31

申请号：EP11827709.4

申请日：2011-09-26

申请人： Intel Corporation

发明人： BAILEY, Abdul, M. ,  TANG, Di ,  ZIMMER, Vincent, J. ,  LI, Kevin, Y. ,  EDWARDS, James, W. ,  KHANNA, Rahul

IPC分类号： G06F13/14

CPC分类号： H04W4/50 ,  G06F9/4401 ,  G06F9/4411 ,  H04W4/60 ,  H04W76/10

摘要： A system, device, and method for facilitating wireless communications during a pre-boot phase of a computing device includes establishing a communications interface between a unified extensible firmware interface executed on the computing device and a wireless transceiver of the computing device during a pre-boot phase of the computing device. An OOB processor of the computing device processes data communications between the unified extensible firmware interface and the wireless communication circuit during the pre-boot phase by reformatting the data communications between wired and wireless communication standards.

公开(公告)号：EP1038227B1

公开(公告)日：2007-08-29

申请号：EP98957992.5

申请日：1998-11-16

申请人： INTEL CORPORATION

发明人： ZIMMER, Vincent, J.

IPC分类号： G06F12/00 ,  G06F11/00

CPC分类号： G06F12/0292 ,  G06F9/32

摘要： The invention relates to the alteration of a segment (230) and an offset (240) used to form an effective address (220) of the default interrupt handler routine. The method comprising a number of steps. First, a trap address (210) of a default interrupt handler routine is provided. This trap address includes a segment (230) and an offset (240) normally used to calculate the effective address (220) via conventional circuitry. However, a unique segment is produced by performing an arithmetic operation on the segment (230). Thereafter, another arithmetic operation is performed to produce a unique offset. These unique segment and offset values may still be used by the conventional circuitry to still produce the same effective addresses so that only one default interrupt handler routine is required. While this alteration produces a unique segment (230) and offset (240) which can be assigned to an interrupt, the segment and offset are modified appropriately to still use a common default interrupt handler.

公开(公告)号：EP1038227A1

公开(公告)日：2000-09-27

申请号：EP98957992.5

申请日：1998-11-16

申请人： INTEL CORPORATION

发明人： ZIMMER, Vincent, J.

IPC分类号： G06F12/00 ,  G06F11/00

CPC分类号： G06F12/0292 ,  G06F9/32

摘要： The invention relates to the alteration of a segment (230) and an offset (240) used to form an effective address (220) of the default interrupt handler routine. The method comprising a number of steps. First, a trap address (210) of a default interrupt handler routine is provided. This trap address includes a segment (230) and an offset (240) normally used to calculate the effective address (220) via conventional circuitry. However, a unique segment is produced by performing an arithmetic operation on the segment (230). Thereafter, another arithmetic operation is performed to produce a unique offset. These unique segment and offset values may still be used by the conventional circuitry to still produce the same effective addresses so that only one default interrupt handler routine is required. While this alteration produces a unique segment (230) and offset (240) which can be assigned to an interrupt, the segment and offset are modified appropriately to still use a common default interrupt handler.

公开(公告)号：EP2619679B1

公开(公告)日：2019-06-19

申请号：EP11827709.4

申请日：2011-09-26

申请人： Intel Corporation

发明人： BAILEY, Abdul, M. ,  TANG, Di ,  ZIMMER, Vincent, J. ,  LI, Kevin, Y. ,  EDWARDS, James, W. ,  KHANNA, Rahul

IPC分类号： G06F9/44 ,  H04W4/00

公开(公告)号：EP2729896B1

公开(公告)日：2019-05-15

申请号：EP12807077.8

申请日：2012-07-05

申请人： Intel Corporation

发明人： HELD, James, P. ,  ROBINSON, Scott, H. ,  ZIMMER, Vincent, J.

IPC分类号： G06F21/57 ,  G06F21/64 ,  G06F9/4401