公开(公告)号：EP0882266A1

公开(公告)日：1998-12-09

申请号：EP97908675.0

申请日：1997-02-19

申请人： Intergraph Corporation

发明人： McKINNEY, Arthur, C. ,  McCARVER, Charles, H., Jr. ,  SAMIEE, Vahid

IPC分类号： G06F12 ,  G06F13 ,  G06F15 ,  H03K19

CPC分类号： G06F12/0813 ,  G06F12/0822 ,  G06F12/0831 ,  G06F13/4022 ,  G06F13/4077 ,  G06F15/173 ,  H03K19/00361 ,  H03K19/018521

摘要： The present invention provides a high-availability parallel processing server that is a multi-processor computer with a segmented memory architecture. The processors are grouped into processor clusters, with each cluster consisting of up to four processors in a preferred embodiment. Each cluster of processors has dedicated memory buses for communicating with each of the memory segments. The invention is designed to be able to maintain coherent interaction between all processors and memory segments within a preferred embodiment. A preferred embodiment uses Intel Pentium-Pro processors. The present invention comprises a plurality of processor segments (a cluster of one or more CPU's) memory segments (separate regions of memory), and memory communication buses (pathways to communicate with the memory segment). Each processor segment has a dedicated communication bus for interacting with each memory segment, allowing different processors parallel access to different memory segments while working in parallel. The processors, in preferred embodiment, may further include an internal cache and flags associated with the cache to allow multi-processor cache coherency in external write-back cache.

公开(公告)号：EP0882265A1

公开(公告)日：1998-12-09

申请号：EP97907688.0

申请日：1997-02-19

申请人： Intergraph Corporation

发明人： BOECKMANN, Eduard, F. ,  BRETHOUR, Vern ,  SAMIEE, Vahid

IPC分类号： G06F12 ,  G06F13 ,  H03K19

CPC分类号： H03K19/018521 ,  G06F12/0822 ,  G06F12/0831 ,  G06F13/4022 ,  G06F13/4077 ,  H03K19/00361

摘要： An output driver for providing bus signals at a driver output in response to an input signal, the driver having a driver input signal responsive to the input signal, a supply voltage terminal and a ground terminal. The driver includes an improved clamping of an initially ON (i.e. high going) output pulse of the driver and adds an active pull-up function inside the integrated circuit that does not change the external circuit nor require additional functional external circuit connections.