公开(公告)号：EP0180022A3

公开(公告)日：1989-03-15

申请号：EP85111751.5

申请日：1985-09-17

申请人： International Business Machines Corporation

发明人： Andersen, John Edward ,  Barry, Robert Lloyd ,  Christie, Kenneth Howard ,  Shea, Dennis John

IPC分类号： G06F15/40 ,  G11C15/04

CPC分类号： G06F17/30982

摘要： The memory system includes a plurality of reconfigurable subarrays of memory cells (SUBO...SUB3) and having the capability of simultaneously performing write/compare, read/compare, compare/bypass, write/bypass, or write/ compare/bypass operations. The present system may be fabricated on a single integrated circuit chip and includes circuitry for selectively writing data into the subarrays (12, WD10...WD18, BDO...BD3, WSO...WS3). Output data from the subarrays (SUBO...SUB3) is connected to compare data logic (CL10...CL13, CL20...CL23) for comparing the subarray data to one or more bytes of compare input data, and to bit select logic (BSO...BS3) for selectively placing the subarray data onto an output bus. Bypass select logic (24) causes either the subarray data or one byte of compare data to be output from the memory system data output port. In one embodiment, two bytes of compare input data can be simultaneously compared with a selected data byte from each of the subarrays (SUBO...SUB3), and one byte of compare input data can be bypassed to the data output port during the compare operation. Additionally, data may be written into the subarrays (SUBO...SUB3) while simultaneously performing the compare or the compare/bypass operations.

公开(公告)号：EP0180022B1

公开(公告)日：1992-11-19

申请号：EP85111751.5

申请日：1985-09-17

申请人： International Business Machines Corporation

发明人： Andersen, John Edward ,  Barry, Robert Lloyd ,  Christie, Kenneth Howard ,  Shea, Dennis John

IPC分类号： G06F15/40 ,  G11C15/04

CPC分类号： G06F17/30982

公开(公告)号：EP0180022A2

公开(公告)日：1986-05-07

申请号：EP85111751.5

申请日：1985-09-17

申请人： International Business Machines Corporation

发明人： Andersen, John Edward ,  Barry, Robert Lloyd ,  Christie, Kenneth Howard ,  Shea, Dennis John

IPC分类号： G06F15/40 ,  G11C15/04

CPC分类号： G06F17/30982

摘要： The memory system includes a plurality of reconfigurable subarrays of memory cells (SUBO...SUB3) and having the capability of simultaneously performing write/compare, read/compare, compare/bypass, write/bypass, or write/ compare/bypass operations. The present system may be fabricated on a single integrated circuit chip and includes circuitry for selectively writing data into the subarrays (12, WD10...WD18, BDO...BD3, WSO...WS3). Output data from the subarrays (SUBO...SUB3) is connected to compare data logic (CL10...CL13, CL20...CL23) for comparing the subarray data to one or more bytes of compare input data, and to bit select logic (BSO...BS3) for selectively placing the subarray data onto an output bus. Bypass select logic (24) causes either the subarray data or one byte of compare data to be output from the memory system data output port. In one embodiment, two bytes of compare input data can be simultaneously compared with a selected data byte from each of the subarrays (SUBO...SUB3), and one byte of compare input data can be bypassed to the data output port during the compare operation. Additionally, data may be written into the subarrays (SUBO...SUB3) while simultaneously performing the compare or the compare/bypass operations.

摘要翻译： 存储器系统包括存储器单元（SUBO ... SUB3）的多个可重新配置的子阵列，并且具有同时执行写入/比较，读取/比较，比较/旁路，写/旁路或写入/比较/旁路操作的能力。 本系统可以在单个集成电路芯片上制造，并且包括用于将数据选择性地写入子阵列（12，WD10 ... WD18，BD0 ... BD3，WS0 ... WS3）的电路。 来自子阵列（SUB0 ... SUB3）的输出数据被连接以比较数据逻辑（CL10 ... CL13，CL20 ... CL23），用于将子阵列数据与比较输入数据的一个或多个字节进行比较，并将位选择 逻辑（BS0 ... BS3），用于选择性地将子阵列数据放置在输出总线上。 旁路选择逻辑（24）导致从存储器系统数据输出端口输出子阵列数据或比较数据的一个字节。 在一个实施例中，两个字节的比较输入数据可以与来自每个子阵列（SUB0 ... SUB3）的所选数据字节同时进行比较，并且比较输入数据的一个字节可以在比较期间被旁路到数据输出端口 操作。 此外，数据可以写入子阵列（SUBO ... SUB3），同时执行比较或比较/旁路操作。