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11 条记录 (耗时 0.012 秒)

    A multiple read/write access memory system
    2.
    发明公开
    A multiple read/write access memory system 失效
    Speicherannnung mit mehrfachem Lese-Schreibzugriff。

    公开(公告)号：EP0224691A2

    公开(公告)日：1987-06-10

    申请号：EP86114207.3

    申请日：1986-10-14

    申请人： International Business Machines Corporation

    发明人： Auerbach, Daniel Jonathan ,  Paul, Wolfgang Jakob ,  Chen, Tien Chi

    IPC分类号： G06F13/16 ,  G06F12/06

    CPC分类号： G06F9/3012 ,  G06F9/345 ,  G06F15/8053

    摘要： A memory system to accommodate two read accesses and one write access in a memory cycle and comprising two groups (11,12) of two independently addressable storage units (126,132; 146,152), each storage unit being addressable by the same spectrum of addresses and each group having a pointer arrangement - (13,14) indicating not more than one storage unit in the group for each address of the spectrum of addresses, by the which it is accessed, together with an input for one of the read addresses and the write address (101,103; 102,103), a data output (129,149) and a data input (133), means (109,124,130; 117. 144,150) to selectively connect the read address connected to a group to that storage unit of the group indicated by the pointer for that address and to selectively connect the data input to the other storage unit, means (128,148) to connect the read storage unit to the data output and means (112,120) to set the pointer for the write address to point to the storage unit of the group used for the writing operation. The generalised case of r reads and w writes is also shown.

    摘要翻译： 一种存储器系统，用于在存储器周期内容纳两个读取访问和一个写访问，并且包括两个可独立寻址的存储单元（126,132; 146,152）的两组（11,12），每个存储单元可由相同的地址频址寻址，并且每个 组具有指示器布置（13,14），其指示对于所访问的地址频谱的每个地址的组中不超过一个存储单元以及用于读取地址和写入地址之一的输入 （101,103; 102,103），数据输出（129,149）和数据输入（133），用于选择性地将连接到组的读取地址连接到由指示器指示的组中的存储单元的装置（109,124,130; 117,144,150） 所述地址并且有选择地将所述数据输入连接到所述另一个存储单元，用于将所述读取存储单元连接到所述数据输出的装置（128,148）和用于将所述写入地址的所述指针设置为指向所述存储单元的装置（112,120） 使用组 用于写作操作。 还会显示r读取和w写入的一般情况。

    A multiple read/write access memory system
    3.
    发明公开
    A multiple read/write access memory system 失效
    多个读/写访问存储系统

    公开(公告)号：EP0224691A3

    公开(公告)日：1989-12-20

    申请号：EP86114207.3

    申请日：1986-10-14

    申请人： International Business Machines Corporation

    发明人： Auerbach, Daniel Jonathan ,  Paul, Wolfgang Jakob ,  Chen, Tien Chi

    IPC分类号： G06F13/16 ,  G06F12/06

    CPC分类号： G06F9/3012 ,  G06F9/345 ,  G06F15/8053

    摘要： A memory system to accommodate two read accesses and one write access in a memory cycle and comprising two groups (11,12) of two independently addressable storage units (126,132; 146,152), each storage unit being addressable by the same spectrum of addresses and each group having a pointer arrangement - (13,14) indicating not more than one storage unit in the group for each address of the spectrum of addresses, by the which it is accessed, together with an input for one of the read addresses and the write address (101,103; 102,103), a data output (129,149) and a data input (133), means (109,124,130; 117. 144,150) to selectively connect the read address connected to a group to that storage unit of the group indicated by the pointer for that address and to selectively connect the data input to the other storage unit, means (128,148) to connect the read storage unit to the data output and means (112,120) to set the pointer for the write address to point to the storage unit of the group used for the writing operation. The generalised case of r reads and w writes is also shown.

    Three address instruction data processing apparatus
    6.
    发明公开
    Three address instruction data processing apparatus 失效
    三地址指令数据处理设备

    公开(公告)号：EP0227900A3

    公开(公告)日：1989-08-16

    申请号：EP86114206.5

    申请日：1986-10-14

    申请人： International Business Machines Corporation

    发明人： Wolfgang, Jakob Paul ,  Auerbach, Daniel Jonathan ,  Chen, Tien Chi

    IPC分类号： G06F9/355 ,  G06F15/00

    CPC分类号： G06F9/355 ,  G06F9/30109 ,  G06F9/345 ,  G06F9/3455 ,  G06F15/8053

    摘要： Scientific data processing apparatus performing three address code operations (102), is responsive to instruction words in successive cycles for generating addresses for a memory (106) storing data objects addressable by r-bit addresses. The memory includes a first (107), a second (109) and a third (112) r-bit address register each having an associated data register (120,125,130) and an associated index register, these latter storing alterable first (118), second (123) and third indices (128) respectively for supply as addresses to the r-bit address registers. Counters (118,123,128) responsive to at least a portion of an instruction word in a cycle independently increment, within the cycle, the indices. Partial base addresses (121,126,131) for the index registers are supplied directly from the instruction word (102). In addition, a means (134) is provided that is responsive to at least a portion of an instruction word in a cycle for independently supplying an arbitrary index within the cycle to at least one of the index registers (118,123,128) to update the corresponding index/indices.

    Three address instruction data processing apparatus
    7.
    发明公开
    Three address instruction data processing apparatus 失效
    Datenverarbeitungsgerätmit Drei-Adress-Befehlen。

    公开(公告)号：EP0227900A2

    公开(公告)日：1987-07-08

    申请号：EP86114206.5

    申请日：1986-10-14

    申请人： International Business Machines Corporation

    发明人： Wolfgang, Jakob Paul ,  Auerbach, Daniel Jonathan ,  Chen, Tien Chi

    IPC分类号： G06F9/355 ,  G06F15/00

    CPC分类号： G06F9/355 ,  G06F9/30109 ,  G06F9/345 ,  G06F9/3455 ,  G06F15/8053

    摘要： Scientific data processing apparatus performing three address code operations (102), is responsive to instruction words in successive cycles for generating addresses for a memory (106) storing data objects addressable by r-bit addresses. The memory includes a first (107), a second (109) and a third (112) r-bit address register each having an associated data register (120,125,130) and an associated index register, these latter storing alterable first (118), second (123) and third indices (128) respectively for supply as addresses to the r-bit address registers. Counters (118,123,128) responsive to at least a portion of an instruction word in a cycle independently increment, within the cycle, the indices. Partial base addresses (121,126,131) for the index registers are supplied directly from the instruction word (102). In addition, a means (134) is provided that is responsive to at least a portion of an instruction word in a cycle for independently supplying an arbitrary index within the cycle to at least one of the index registers (118,123,128) to update the corresponding index/indices.

    摘要翻译： 执行三个地址码操作（102）的科学数据处理装置响应于连续循环中的指令字，以产生用于存储可由r位地址寻址的数据对象的存储器（106）的地址。 存储器包括第一（107），第二（109）和第三（112）r位地址寄存器，每个地址寄存器具有相关联的数据寄存器（120,125,130）和相关联的索引寄存器，后者存储可变的第一（118），第二 （123）和第三索引（128）分别作为地址提供给r位地址寄存器。 响应于循环中的指令字的至少一部分的计数器（118,123,128）在周期内独立地增加索引。 索引寄存器的部分基址（121,126,131）直接从指令字（102）提供。 另外，提供了一种装置（134），其响应于循环中的指令字的至少一部分，用于独立地向循环内的任意索引提供至少一个索引寄存器（118,123,128）以更新相应的索引 /指数。