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1.发明公开Structure and process for fabrication of stacked complementary MOS field effect transistor devices 失效结构和制造过程为堆叠互补MOS场效应晶体管的阵列。
公开(公告)号：EP0066068A2
公开(公告)日：1982-12-08
申请号：EP82103172.1
申请日：1982-04-15
CPC分类号： H01L21/8238 , H01L21/268 , H01L27/0688 , H01L27/0922 , H01L29/04
摘要： A method for fabricating a stacked complementary MOSFET device comprising the steps of:
depositing a layer of phosphosilicate glass (58) on top of the gate electrode (56) of an N channel FET device (4) formed in the surface of a monocrystalline silicon substrate (50) having source (60) and drain (62) diffusions in said substrate on either side of said gate; depositing a layer of P-type polycrystalline silicon (65) over said phosphosilicate glass layer (58), extending over said source (60) and drain (62) diffusions and physically contacting a portion of the surface of said monocrystalline silicon substrate (50);
heating said polycrystalline silicon layer (65) including said portion contacting said substrate (50) to a recrystallization temperature;
cooling and recrystallizing said polycrystalline silicon layer (65) into a monocrystalline silicon form having a lattice orientation epitaxially reoriented to the lattice orientation of said monocrystalline semiconductor substrate (50);
heating said phosphosilicate glass layer (58) so as to diffuse phosphorous atoms from said phosphosilicate glass layer upwardly into said silicon layer (65), forming an N-type region (78) which is juxtaposed with said gate electrode (56) and is self-aligned to said gate electrode.
The structure of the complementary MOSFET device comprises an upper, P channel FET device (6) which is formed in said silicon layer (65), and which shares said gate electrode (56) with said N channel FET device (4).摘要翻译： （4）而形成沉积磷硅酸盐玻璃（58）的上的N沟道FET器件的栅电极（56）的顶部上的层中的单晶硅衬底的表面：一种用于制造堆叠的互补MOSFET器件，包括以下步骤的方法 （50），其具有源极（60）和漏极（62）中在所述栅极的任一侧所说基片扩散; 沉积在所述p型多晶硅（65）的层磷硅酸盐延伸在所述源（60）和漏极（62）扩散的玻璃层（58）上和物理上接触所述单晶硅衬底的表面（50）的部分 ; 所述包括所述部分接触所述基板（50），以再结晶温度加热多晶硅层（65）; 冷却和重结晶所述多晶硅层（65）为具有晶格取向外延重新定向到所述单晶半导体衬底的晶格取向（50）单晶硅模具; 加热所述磷硅酸盐玻璃层（58），以扩散磷原子从所述磷硅酸盐玻璃层向上到所述硅层，其与所述栅电极（56）并置并且是自（65）形成的N型区（78）的所有 -aligned到所述栅电极。 的上部的互补MOSFET器件包括的结构中，P沟道FET器件（6），所有这些是在形成于所述硅层（65）和这股所述栅电极（56）与所述N沟道FET器件（4）。
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2.发明授权Structure and process for fabrication of stacked complementary MOS field effect transistor devices 失效堆叠的补充MOS场效应晶体管器件的结构和工艺
公开(公告)号：EP0066068B1
公开(公告)日：1988-11-02
申请号：EP82103172.1
申请日：1982-04-15
CPC分类号： H01L21/8238 , H01L21/268 , H01L27/0688 , H01L27/0922 , H01L29/04
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3.发明公开Structure and process for fabrication of stacked complementary MOS field effect transistor devices 失效堆叠补充MOS场效应晶体管器件的结构和工艺
公开(公告)号：EP0066068A3
公开(公告)日：1985-09-18
申请号：EP82103172
申请日：1982-04-15
CPC分类号： H01L21/8238 , H01L21/268 , H01L27/0688 , H01L27/0922 , H01L29/04
摘要： A method for fabricating a stacked complementary MOSFET device comprising the steps of:
depositing a layer of phosphosilicate glass (58) on top of the gate electrode (56) of an N channel FET device (4) formed in the surface of a monocrystalline silicon substrate (50) having source (60) and drain (62) diffusions in said substrate on either side of said gate; depositing a layer of P-type polycrystalline silicon (65) over said phosphosilicate glass layer (58), extending over said source (60) and drain (62) diffusions and physically contacting a portion of the surface of said monocrystalline silicon substrate (50); heating said polycrystalline silicon layer (65) including said portion contacting said substrate (50) to a recrystallization temperature; cooling and recrystallizing said polycrystalline silicon layer (65) into a monocrystalline silicon form having a lattice orientation epitaxially reoriented to the lattice orientation of said monocrystalline semiconductor substrate (50); heating said phosphosilicate glass layer (58) so as to diffuse phosphorous atoms from said phosphosilicate glass layer upwardly into said silicon layer (65), forming an N-type region (78) which is juxtaposed with said gate electrode (56) and is self-aligned to said gate electrode. The structure of the complementary MOSFET device comprises an upper, P channel FET device (6) which is formed in said silicon layer (65), and which shares said gate electrode (56) with said N channel FET device (4).
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