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1.发明公开An arithmetic logic unit for a graphics processor 失效Arithmetisch logische Einheitfüreinen Grafikprozessor。
公开(公告)号：EP0385568A2
公开(公告)日：1990-09-05
申请号：EP90300502.3
申请日：1990-01-18
发明人： Bates, Mathew Damien , West, Roderick Michael , Gay, Adrian Charles , Butler, Nichola David , Kim, Jong Han
IPC分类号： G06F7/50
CPC分类号： G06F7/505 , G06F9/30036 , G06F2207/3816 , G06F2207/3828
摘要： A digital arithmetic logic unit is described in which the carry chain (6) is subdivided into a series of bit-fields allowing independent and simultaneous data manipulation to be undertaken in each of the bit-fields. Division of the carry chain is achieved via a carry chain selector (7) consisting of a series of multiplexers (9), one being placed between each stage (FA) of the carry chain. Each multiplexer has two data inputs, one of which forms the carry to the next stage of the carry chain. The carry selected either continues the computation or defines the end of the bit-field and forms the least significant bit of the next bit-field. This selection of the carry by the multiplexer is under control of a programmable register (8), thus allowing variable division of the carry chain.
摘要翻译： 描述了数字算术逻辑单元，其中进位链（6）被细分为一系列位域，允许在每个位域中进行独立且同时的数据操作。 通过由一系列多路复用器（9）组成的进位链选择器（7）实现进位链的分割，一个放置在进位链的每个阶段（FA）之间。 每个复用器具有两个数据输入，其中一个形成进位链的下一个进位。 选择的进位可以继续计算或定义位域的结束，并形成下一个位域的最低有效位。 多路复用器的进位选择在可编程寄存器（8）的控制下，从而允许进位链的可变划分。
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公开(公告)号：EP0385568A3
公开(公告)日：1992-04-22
申请号：EP90300502.3
申请日：1990-01-18
发明人： Bates, Mathew Damien , West, Roderick Michael , Gay, Adrian Charles , Butler, Nichola David , Kim, Jong Han
IPC分类号： G06F7/50
CPC分类号： G06F7/505 , G06F9/30036 , G06F2207/3816 , G06F2207/3828
摘要： A digital arithmetic logic unit is described in which the carry chain (6) is subdivided into a series of bit-fields allowing independent and simultaneous data manipulation to be undertaken in each of the bit-fields. Division of the carry chain is achieved via a carry chain selector (7) consisting of a series of multiplexers (9), one being placed between each stage (FA) of the carry chain. Each multiplexer has two data inputs, one of which forms the carry to the next stage of the carry chain. The carry selected either continues the computation or defines the end of the bit-field and forms the least significant bit of the next bit-field. This selection of the carry by the multiplexer is under control of a programmable register (8), thus allowing variable division of the carry chain.
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