Method of making complementary field effect transistors
    1.
    发明公开
    Method of making complementary field effect transistors 失效
    制作补充场效应晶体管的方法

    公开(公告)号:EP0087573A3

    公开(公告)日:1986-09-17

    申请号:EP83100523

    申请日:1983-01-21

    IPC分类号: H01L21/82

    摘要: A method is provided for making complementary field effect transistors in a semiconductor layer having a first portion including an N type transistor with a channel region defined by N+ source and drain regions (30', 32') and having a second portion including a P type transistor with a channel region defined by P+ source and drain regions (40, 42). An insulating layer (44) is disposed over the first and second portions with thin insulating films formed over the channel regions. The steps of the method include applying a masking layer (46) over the insulating layer (44) having an opening over one of the portions, introducing a first impurity (1/11) into the channel region of the one portion for channel tailoring purposes, depositing a first conductive refractory material (50) on the thin insulating film located over the channel region of the one portion, removing the masking layer (46), introducing a second impurity (1/12) into the channel region of the other portion for channel tailoring purposes and depositing a second conductive material (56) on the thin insulating film located over the channel region of the other portion and in contact with the first conductive material (50). The first and second conductive materials (50, 56) have different work functions.

    Method of making complementary field effect transistors
    3.
    发明公开
    Method of making complementary field effect transistors 失效
    制造互补场效应晶体管的方法。

    公开(公告)号:EP0087573A2

    公开(公告)日:1983-09-07

    申请号:EP83100523.6

    申请日:1983-01-21

    IPC分类号: H01L21/82

    摘要: A method is provided for making complementary field effect transistors in a semiconductor layer having a first portion including an N type transistor with a channel region defined by N+ source and drain regions (30', 32') and having a second portion including a P type transistor with a channel region defined by P+ source and drain regions (40, 42).
    An insulating layer (44) is disposed over the first and second portions with thin insulating films formed over the channel regions. The steps of the method include applying a masking layer (46) over the insulating layer (44) having an opening over one of the portions, introducing a first impurity (1/11) into the channel region of the one portion for channel tailoring purposes, depositing a first conductive refractory material (50) on the thin insulating film located over the channel region of the one portion, removing the masking layer (46), introducing a second impurity (1/12) into the channel region of the other portion for channel tailoring purposes and depositing a second conductive material (56) on the thin insulating film located over the channel region of the other portion and in contact with the first conductive material (50). The first and second conductive materials (50, 56) have different work functions.