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公开(公告)号：EP0238836A2
公开(公告)日：1987-09-30
申请号：EP87102194.5
申请日：1987-02-17
IPC分类号： H01L21/31 , H01L21/76 , H01L27/10 , H01L21/312
CPC分类号： H01L21/76237 , H01L21/743
摘要： A method is provided for making a semiconductor structure which includes the steps of forming in a semiconductor body a P/N junction and a first opening (50, 54) in a first insulating layer (42) disposed on the surface of the semiconductor body. A trench (22) is then formed in the semiconductor body having a sidewall located along a given plane through the opening and through the P/N junction. A second layer of insulation (56) is formed within the opening and on the sidewall of the trench. An insulating material (24) is disposed within the trench (22) and over the second insulating layer (56) in the opening and a block (62) or segment of material is located over the trench (22) so as to extend a given distance from the trench over the upper surface of the body. The insulating material (24) and the block (62) are then etched so as to remove the block and the insulating material along the sides of the block. The exposed portions of the second insulating layer (56) are now etched to form a second opening therein within the first opening (50, 54) in the first insulating layer (42). A layer (64) of low viscosity material, such as a photoresist, is formed over the semiconductor body so as to cover the remaining portion of the insulating material (24), the layer (64) of low viscosity material and the insulating material (24) having similar etch rates. The layer (64) of low viscosity material and the insulating material (24) are then simultaneously etched directionally, e.g., by a reactive ion etching process (RIE), until all of the layer (64) of low viscosity material is removed to at least the surface of the second insulating layer (56) at the trench (22). Any suitable wet etchant may then be used, if desired, to remove any remaining low viscosity material disposed within the second opening in the second insulating layer. Metallic contacts (W T , W B , B O ) may now be formed, e.g., by evaporation, on the surface of the semiconductor body within the second opening in the second insulating layer without the concern that the metallic material will seep or enter into the trench causing a short at the P/N junction.
In a preferred embodiment of the invention, the insulating material (24) is polyimide and the block (62) of material, as well as the layer (64) of low viscosity material, is made of photoresist.摘要翻译： 提供了一种用于制造半导体结构，其包括在半导体本体中形成设置在所述半导体主体的表面上的P / N结，并在第一绝缘层（42）的第一开口（50，54）的步骤的方法。 沟槽（22）然后，在具有通过所述开口，并通过P / N结沿给定平面位于一个侧壁的半导体本体形成。 绝缘（56）的第二层在所述开口内并且在所述沟槽的侧壁形成。 绝缘材料（24）被所述沟槽（22）内设置与在开口中的第二绝缘层（56）和块（62）或材料的段超过位于所述沟槽（22），从而延长给定 从沟槽在所述主体的上表面的距离。 然后，将绝缘材料（24）和所述块（62）被蚀刻，从而去除块和沿着块的侧面的绝缘材料。 在第二绝缘层（56）的暴露部分被蚀刻现在以在其中形成第一绝缘层（42）在第一开口（50，54）内的第二开口。 低粘度材料，颜色的层（64）：如光致抗蚀剂，在半导体本体形成为覆盖绝缘材料（24）的剩余部分，低粘度材料的层（64）和绝缘材料（ 24）具有类似的蚀刻速率。 低粘度材料的层（64）和绝缘材料（24）然后同时定向蚀刻，例如通过反应离子蚀刻工艺（RIE），直到所有的低粘度材料的层（64）的被去除，以在 在沟槽（22）在第二绝缘层（56）的至少表面上。 任何适合的湿法蚀刻剂然后可用于，如果需要清除，以除去第二绝缘层中的第二开口内设置任何剩余的低粘度材料。 金属接触（WT，WB，BO）现在可以形成的，例如，通过蒸发，在半导体本体的表面上的第二绝缘层中的第二开口，而不关心内并在金属材料将渗入或进入沟槽曹景伟 短在P / N结。 ... 在本发明的一个优选实施方案中，绝缘材料（24）是聚酰亚胺和材料块（62），以及低粘度材料的层（64），由光致抗蚀剂。
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公开(公告)号：EP0042084A1
公开(公告)日：1981-12-23
申请号：EP81104003.9
申请日：1981-05-25
CPC分类号： H01L29/7827 , H01L21/76877 , H01L27/10841
摘要： High density V-MOSFET device, particularly single transistor memory cells, are provided by use of a series of simplified self-aligning process steps. Gate electrodes, source/drain regions and source/drain contacts are provided with the aid of an initial mask-less photoresist removal process in which a relatively thick layer of self-leveling photoresist is uniformly removed in order to define portions of a gate electrode within the recess of a V-groove. The gate electrode (22) subsequently acts as a self-aligned mask to define implanted source/drain regions (30, 32) also within the V-groove (18) and to enable second level interconnecting metallurgy contacts (34) to be formed along the sidewalls of the V-groove (18) below the level of the surface of the substrate (10, 14).
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公开(公告)号：EP0238836A3
公开(公告)日：1987-12-02
申请号：EP87102194
申请日：1987-02-17
IPC分类号： H01L21/31 , H01L21/76 , H01L27/10 , H01L21/312
CPC分类号： H01L21/76237 , H01L21/743
摘要： A method is provided for making a semiconductor structure which includes the steps of forming in a semiconductor body a P/N junction and a first opening (50, 54) in a first insulating layer (42) disposed on the surface of the semiconductor body. A trench (22) is then formed in the semiconductor body having a sidewall located along a given plane through the opening and through the P/N junction. A second layer of insulation (56) is formed within the opening and on the sidewall of the trench. An insulating material (24) is disposed within the trench (22) and over the second insulating layer (56) in the opening and a block (62) or segment of material is located over the trench (22) so as to extend a given distance from the trench over the upper surface of the body. The insulating material (24) and the block (62) are then etched so as to remove the block and the insulating material along the sides of the block. The exposed portions of the second insulating layer (56) are now etched to form a second opening therein within the first opening (50, 54) in the first insulating layer (42). A layer (64) of low viscosity material, such as a photoresist, is formed over the semiconductor body so as to cover the remaining portion of the insulating material (24), the layer (64) of low viscosity material and the insulating material (24) having similar etch rates. The layer (64) of low viscosity material and the insulating material (24) are then simultaneously etched directionally, e.g., by a reactive ion etching process (RIE), until all of the layer (64) of low viscosity material is removed to at least the surface of the second insulating layer (56) at the trench (22). Any suitable wet etchant may then be used, if desired, to remove any remaining low viscosity material disposed within the second opening in the second insulating layer. Metallic contacts (W T , W B , B O ) may now be formed, e.g., by evaporation, on the surface of the semiconductor body within the second opening in the second insulating layer without the concern that the metallic material will seep or enter into the trench causing a short at the P/N junction. In a preferred embodiment of the invention, the insulating material (24) is polyimide and the block (62) of material, as well as the layer (64) of low viscosity material, is made of photoresist.
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公开(公告)号：EP0087573A2
公开(公告)日：1983-09-07
申请号：EP83100523.6
申请日：1983-01-21
IPC分类号： H01L21/82
CPC分类号： H01L21/823842 , H01L27/12 , H01L29/4908 , H01L29/4975
摘要： A method is provided for making complementary field effect transistors in a semiconductor layer having a first portion including an N type transistor with a channel region defined by N+ source and drain regions (30', 32') and having a second portion including a P type transistor with a channel region defined by P+ source and drain regions (40, 42).
An insulating layer (44) is disposed over the first and second portions with thin insulating films formed over the channel regions. The steps of the method include applying a masking layer (46) over the insulating layer (44) having an opening over one of the portions, introducing a first impurity (1/11) into the channel region of the one portion for channel tailoring purposes, depositing a first conductive refractory material (50) on the thin insulating film located over the channel region of the one portion, removing the masking layer (46), introducing a second impurity (1/12) into the channel region of the other portion for channel tailoring purposes and depositing a second conductive material (56) on the thin insulating film located over the channel region of the other portion and in contact with the first conductive material (50). The first and second conductive materials (50, 56) have different work functions.-
公开(公告)号：EP0254046A1
公开(公告)日：1988-01-27
申请号：EP87108924.9
申请日：1987-06-23
IPC分类号： H01L27/10
CPC分类号： H01L27/10841
摘要： A memory is provided which includes a semiconductor substrate (26) having a major surface and a trench (24) disposed therein having a longitudinal axis, storage means (16, 16ʹ) disposed on a given sidewall of the trench, switching means (12, 12ʹ) having a control element and a current carrying element disposed on the given sidewall of the trench between the storage means and the major surface of the substrate and coupled to the storage means, a first electrically conductive line (40, 40ʹ) disposed on the given sidewall in contact with the control element of the switching means and having a longitudinal axis arranged parallel to the longitudinal axis of the trench, and a second electrically conductive line (22, 22ʹ) disposed on the major surface of the semiconductor substrate in contact with the current carrying electrode of the switching means and having a longitudinal axis arranged orthogonal to the longitudinal axis of the trench.
摘要翻译： 提供一种存储器，其包括具有主表面和设置在其中的具有纵向轴线的沟槽（24）的半导体衬底（26），设置在沟槽给定侧壁上的存储装置（16,16'），开关装置 具有控制元件和载流元件的第一导电线（40,40'），所述控制元件和载流元件设置在所述存储装置与所述衬底的所述主表面之间的所述沟槽的所述给定侧壁上并耦合到所述存储装置， 给定的侧壁与开关装置的控制元件接触并且具有平行于沟槽的纵向轴线设置的纵向轴线以及设置在半导体衬底的主表面上的第二导电线路（22,22'），所述第二导电线路 开关装置的载流电极并且具有与沟槽的纵向轴线垂直布置的纵向轴线。
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公开(公告)号：EP0087573A3
公开(公告)日：1986-09-17
申请号：EP83100523
申请日：1983-01-21
IPC分类号： H01L21/82
CPC分类号： H01L21/823842 , H01L27/12 , H01L29/4908 , H01L29/4975
摘要： A method is provided for making complementary field effect transistors in a semiconductor layer having a first portion including an N type transistor with a channel region defined by N+ source and drain regions (30', 32') and having a second portion including a P type transistor with a channel region defined by P+ source and drain regions (40, 42). An insulating layer (44) is disposed over the first and second portions with thin insulating films formed over the channel regions. The steps of the method include applying a masking layer (46) over the insulating layer (44) having an opening over one of the portions, introducing a first impurity (1/11) into the channel region of the one portion for channel tailoring purposes, depositing a first conductive refractory material (50) on the thin insulating film located over the channel region of the one portion, removing the masking layer (46), introducing a second impurity (1/12) into the channel region of the other portion for channel tailoring purposes and depositing a second conductive material (56) on the thin insulating film located over the channel region of the other portion and in contact with the first conductive material (50). The first and second conductive materials (50, 56) have different work functions.
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公开(公告)号：EP0115035A3
公开(公告)日：1986-01-29
申请号：EP83112888
申请日：1983-12-21
发明人： Cottrell, Peter Edwin , Garnache, Richard Raymond , Geipel, Henry John, Jr. , Troutman, Ronald Roy
CPC分类号： H01L23/552 , H01L23/291 , H01L2924/0002 , H01L2924/00
摘要： A radiation tolerant semiconductor structure comprising a plurality of active field effect transistor portions (12, 18) electrically insulated by an insulating structure (25). The insulating structure comprises a plurality of insulating layers (26, 27). The number of these layers and their selective dielectric constants and thicknesses are chosen to reduce the effect of ionizing radiation on the electrical insulation of the active field effect transistor portions.
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8.发明公开Process for putting a self-aligning gate electrode in a V-MOS field-effect transistor 失效用于在V-MOS场效应晶体管中引脚自校正门电极的工艺
公开(公告)号：EP0030640A3
公开(公告)日：1985-11-21
申请号：EP80107215
申请日：1980-11-20
IPC分类号： H01L21/28 , H01L21/306
CPC分类号： H01L29/66621 , H01L21/30608
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9.发明公开Semiconductor structure tolerant to ionizing radiation 失效Halbleiterstruktur mit Resistenz gegen ionisierende Strahlung。
公开(公告)号：EP0115035A2
公开(公告)日：1984-08-08
申请号：EP83112888.9
申请日：1983-12-21
发明人： Cottrell, Peter Edwin , Garnache, Richard Raymond , Geipel, Henry John, Jr. , Troutman, Ronald Roy
CPC分类号： H01L23/552 , H01L23/291 , H01L2924/0002 , H01L2924/00
摘要： A radiation tolerant semiconductor structure comprising a plurality of active field effect transistor portions (12, 18) electrically insulated by an insulating structure (25). The insulating structure comprises a plurality of insulating layers (26, 27). The number of these layers and their selective dielectric constants and thicknesses are chosen to reduce the effect of ionizing radiation on the electrical insulation of the active field effect transistor portions.
摘要翻译： 一种耐辐射半导体结构，包括由绝缘结构（25）电绝缘的多个有源场效应晶体管部分（12,18）。 绝缘结构包括多个绝缘层（26,27）。 选择这些层的数量及其选择性介电常数和厚度以减小电离辐射对有源场效应晶体管部分的电绝缘的影响。
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10.发明公开Verfahren zum Anbringen einer selbstausrichtenden Gateelektrode in einem V-Metalloxid-Feldeffekttransistor 失效在V型金属氧化物场效应晶体管附加自对准栅极电极的方法。
公开(公告)号：EP0030640A2
公开(公告)日：1981-06-24
申请号：EP80107215.8
申请日：1980-11-20
IPC分类号： H01L21/28 , H01L21/306
CPC分类号： H01L29/66621 , H01L21/30608
摘要： Verfahren zum Herstellen von selbstausgerichteten Leitern in vertikalen, integrierten Halbleitervorrichtungen mit V-förmigen, oder rechteckigen Vertiefungen auf einer Oberfläche eines Halbleitersubstrats durch Niederschlagen einer leitenden Schicht über der Oberfläche einschließlich der Vertiefung, und Aufbringen eines eine Maske bildenden Materials über der leitenden Schicht bis eine ebene Oberfläche gebildet ist, sowie durch selektives Abätzen der Maskenschicht, bis nur noch eine Maskenschicht innerhalb der Vertiefung verbleibt und anschließend durch selektives Abätzen der danach freiliegendenTeileder leitenden Schicht.
摘要翻译： 通过沉积在表面上的导电层，其包括凹部产生在与半导体基板的表面上的V形，或矩形的孔垂直集成的半导体器件自吸面向导体，并施加一个掩模形成材料的导电层上的电平的方法 表面被选择性地蚀刻导电层的随后暴露部分形成并通过选择性地蚀刻掩模层保留，直到凹部内仅一个掩模层，然后。
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