-
公开(公告)号：EP0058845B1
公开(公告)日：1989-05-10
申请号：EP82100719.2
申请日：1982-02-02
IPC分类号： G11C11/40
CPC分类号： H01L27/1025 , G11C11/411 , G11C11/4116 , G11C11/414 , H03K3/288
-
公开(公告)号：EP0087510A1
公开(公告)日：1983-09-07
申请号：EP82111119.2
申请日：1982-12-02
发明人： Eardley, David Barry
IPC分类号： H03K3/033
CPC分类号： H03K3/033
摘要： A multivibrator comprising two inverting OR circuits (1', 2') connected in closed loop configuration by a cascaded series of delaying elements (11, 12, 13) some of which are partially bypassed at selected locations so as to reduce the recovery time of the multivibrator. The delaying elements comprise one or more inverting OR circuits (13) positioned at the selected locations with the remainder being simple inverting circuits. Although the output pulse width of the multivibrator is determined by the total delay of the cascaded units, the recovery time is made a fraction thereof, depending upon the number and the locations of the bypasses.
摘要翻译： 一种多谐振荡器，包括通过级联的一系列延迟元件（11,12,13）以闭环配置连接的两个反相OR电路（1分钟，2分钟），其中一些延迟元件在选定位置被部分旁路以便减少恢复时间 多谐振荡器。 延迟元件包括位于选定位置的一个或多个反相OR电路（13），其余部分是简单的反相电路。 尽管多谐振荡器的输出脉冲宽度由级联单元的总延迟确定，但是根据旁路的数量和位置，恢复时间是其一部分。
-
公开(公告)号：EP0058845A2
公开(公告)日：1982-09-01
申请号：EP82100719.2
申请日：1982-02-02
IPC分类号： G11C11/40
CPC分类号： H01L27/1025 , G11C11/411 , G11C11/4116 , G11C11/414 , H03K3/288
摘要： Two memory cells each can be entirely fabricated in only two isolation beds. In one embodiment each bed contains one lateral PNP (64, 66) and one vertical NPN transistor (60, 62) in a merged structure. In a second embodiment, each bed contains one lateral PNP (118, 120) and two vertical NPN transistors (110, 122; 112, 124) in a merged structure. Memory access circuitry provides a high ratio of selected to unselected cell current in order to permit fast memory operation.
-
公开(公告)号：EP0041603B1
公开(公告)日：1984-07-11
申请号：EP81102886.9
申请日：1981-04-15
发明人： Eardley, David Barry
IPC分类号： G11C17/06
-
公开(公告)号：EP0072414B1
公开(公告)日：1988-01-13
申请号：EP82105776.7
申请日：1982-06-29
CPC分类号： H01L27/1028 , G11C11/34
-
公开(公告)号：EP0087510B1
公开(公告)日：1986-10-22
申请号：EP82111119.2
申请日：1982-12-02
发明人： Eardley, David Barry
IPC分类号： H03K3/033
CPC分类号： H03K3/033
-
公开(公告)号：EP0072414A3
公开(公告)日：1986-06-11
申请号：EP82105776
申请日：1982-06-29
CPC分类号： H01L27/1028 , G11C11/34
摘要： A single device dynamic semiconductor memory is formed having a P-type conductivity injector region (72) with hligh-low-high junctions of N-type conductivity disposed below the injector region. Those junctions trap injected minority charges which are detected by sensing the current flow from a source region (68) to a drain regions (51) which are located on opposite sides of the injector region (72). The source (68) and injector region (72) utilize ohmic contact while the low barrier Schottky contact (80) is made to the drain region (51). in order to provide separation between the depletion region of the Schottky contact (80) and the injector region (72), a heavily doped N (22) region is provided.
摘要翻译： 单个器件动态半导体存储器形成为具有设置在注入区下方的具有N型导电性的高 - 低 - 高结的P型导电注入区（72）。 那些结俘获注入的少数电荷，这些少数电荷通过感测从源区域（68）到位于注入区域（72）的相对侧上的漏极区域（51）的电流而被检测到。 源极（68）和注入区（72）利用欧姆接触，而低阻挡肖特基接触（80）形成于漏极区（51）。 为了提供肖特基接触（80）的耗尽区与注入区（72）之间的分隔，提供重掺杂N（22）区。
-
公开(公告)号：EP0058845A3
公开(公告)日：1986-03-19
申请号：EP82100719
申请日：1982-02-02
IPC分类号： G11C11/40
CPC分类号： H01L27/1025 , G11C11/411 , G11C11/4116 , G11C11/414 , H03K3/288
摘要： Two memory cells each can be entirely fabricated in only two isolation beds. In one embodiment each bed contains one lateral PNP (64, 66) and one vertical NPN transistor (60, 62) in a merged structure. In a second embodiment, each bed contains one lateral PNP (118, 120) and two vertical NPN transistors (110, 122; 112, 124) in a merged structure. Memory access circuitry provides a high ratio of selected to unselected cell current in order to permit fast memory operation.
-
公开(公告)号：EP0072414A2
公开(公告)日：1983-02-23
申请号：EP82105776.7
申请日：1982-06-29
CPC分类号： H01L27/1028 , G11C11/34
摘要： A single device dynamic semiconductor memory is formed having a P-type conductivity injector region (72) with hligh-low-high junctions of N-type conductivity disposed below the injector region. Those junctions trap injected minority charges which are detected by sensing the current flow from a source region (68) to a drain regions (51) which are located on opposite sides of the injector region (72). The source (68) and injector region (72) utilize ohmic contact while the low barrier Schottky contact (80) is made to the drain region (51). in order to provide separation between the depletion region of the Schottky contact (80) and the injector region (72), a heavily doped N (22) region is provided.
摘要翻译： 形成具有设置在注射器区域下方的具有N型导电体的高低接合点的P型电导率注入区域（72）的单一器件动态半导体存储器。 这些接合捕获注入的少量电荷，这些电荷通过感测从源极区域（68）到位于注入器区域（72）的相对侧上的漏极区域（51）的电流来检测。 源极（68）和注入器区域（72）利用欧姆接触，同时将低阻挡肖特基接触（80）制成漏极区域（51）。 为了提供肖特基接触（80）的耗尽区与喷射区（72）之间的分离，提供了重掺杂的N（22）区域。
-
公开(公告)号：EP0041603A1
公开(公告)日：1981-12-16
申请号：EP81102886.9
申请日：1981-04-15
发明人： Eardley, David Barry
IPC分类号： G11C17/06
摘要： This matrix has high barrier Schottky diodes (31, 32) at Read or Reproduce Only Storage (ROS) matrix crossovers to represent 1's (the absence of diodes representing 0's) and low barrier Schottky diodes (90,91) connected to select individual column or bit lines (20,21) of the ROS matrix. A current sink (80,81) is connected to each column. Any unselected column causes the current in that column to be diverted through the respective low barrier diode, thus preventing that current from flowing into the selected row orword line (0,1). The only current that flows into the selected word line of a matrix depends on the single selected column current source.
-
-
-
-
-
-
-
-
-
搜索结果
10 条记录 (耗时 0.01 秒)
