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公开(公告)号：EP3149734A4
公开(公告)日：2017-11-01
申请号：EP15843591
申请日：2015-09-25
申请人： KILOPASS TECH INC
IPC分类号： G11C11/39 , G11C11/41 , G11C11/411 , G11C11/412 , G11C11/419 , H01L21/8249 , H01L27/06 , H01L27/08 , H01L27/082 , H01L27/102 , H01L27/11
CPC分类号： H01L27/1025 , G11C11/39 , G11C11/41 , G11C11/411 , G11C11/412 , G11C11/419 , H01L21/768 , H01L21/8229 , H01L21/8249 , H01L23/528 , H01L27/0623 , H01L27/0821 , H01L27/0826 , H01L27/1027 , H01L27/11 , H01L27/1104 , H01L29/0642 , H01L29/0804 , H01L29/0821 , H01L29/083 , H01L29/1004 , H01L29/1012 , H01L29/1095 , H01L29/7436 , H01L2924/0002 , H01L2924/00
摘要： A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.
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2.发明公开SIX-TRANSISTOR SRAM SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATION 审中-公开SRAM-HALBLEITERSTRUKTURENFÜR六极体在VERFAHREN ZUR HERSTELLUNG
公开(公告)号：EP3149734A1
公开(公告)日：2017-04-05
申请号：EP15843591.7
申请日：2015-09-25
IPC分类号： G11C7/00
CPC分类号： H01L27/1025 , G11C11/39 , G11C11/41 , G11C11/411 , G11C11/412 , G11C11/419 , H01L21/76229 , H01L21/768 , H01L21/8229 , H01L21/8249 , H01L23/528 , H01L27/0623 , H01L27/0821 , H01L27/0826 , H01L27/1027 , H01L27/11 , H01L27/1104 , H01L29/0642 , H01L29/0649 , H01L29/0804 , H01L29/0821 , H01L29/083 , H01L29/1004 , H01L29/1012 , H01L29/1095 , H01L29/42304 , H01L29/6625 , H01L29/66272 , H01L29/735 , H01L29/737 , H01L29/7436 , H01L2924/0002 , H01L2924/00
摘要： A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.
摘要翻译： 基于用于SRAM集成电路的晶闸管的双晶体管存储单元及其制造方法一起被描述。 存储器单元可以以具有浅沟槽隔离的半导体衬底中的晶闸管与MOS和双极选择晶体管的不同组合或不具有选择晶体管来实现。 标准CMOS工艺技术可用于制造SRAM。
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公开(公告)号：EP0367703A3
公开(公告)日：1991-05-29
申请号：EP89480146.3
申请日：1989-09-26
IPC分类号： G11C8/00 , G11C11/412
CPC分类号： G11C8/16 , G11C11/411 , G11C11/412
摘要： The present invention relates to a memory cell, and more particularly to a single-bit, dual-port cell, and a single-sided read circuit for use with one or more such cells. The cell may, in one embodiment, be used in a static random access memory (RAM) array, and may be implemented in BICMOS technology on an integrated circuit. The cell has a flip-flop storage unit (10) comprising a CMOS circuit of cross-coupled inverters coupled to dual CMOS pass gates (12, 22) to provide isolation and data transfer. The storage unit is also coupled to a bipolar read line driver (44) in a particular configuration to accomplish rapid bit line pull-up or pull-down for high speed read operation. Several alternative embodiments are disclosed.
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公开(公告)号：EP0058845A3
公开(公告)日：1986-03-19
申请号：EP82100719
申请日：1982-02-02
IPC分类号： G11C11/40
CPC分类号： H01L27/1025 , G11C11/411 , G11C11/4116 , G11C11/414 , H03K3/288
摘要： Two memory cells each can be entirely fabricated in only two isolation beds. In one embodiment each bed contains one lateral PNP (64, 66) and one vertical NPN transistor (60, 62) in a merged structure. In a second embodiment, each bed contains one lateral PNP (118, 120) and two vertical NPN transistors (110, 122; 112, 124) in a merged structure. Memory access circuitry provides a high ratio of selected to unselected cell current in order to permit fast memory operation.
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公开(公告)号：EP0025502B1
公开(公告)日：1984-02-08
申请号：EP80104533.7
申请日：1980-07-31
CPC分类号： H03K3/288 , G11C11/411 , H03K3/013
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公开(公告)号：EP0025502A1
公开(公告)日：1981-03-25
申请号：EP80104533.7
申请日：1980-07-31
CPC分类号： H03K3/288 , G11C11/411 , H03K3/013
摘要： In einer Kippschaltung mit einem ersten (10) und einem zweiten (12) Stromverteilungsschalter werden Störsignalspitzen am Ausgang der Kippschaltung dadurch verhindert, daß die Eingangstransistoren (32, 50) der beiden Stromverteilungsschalter über einen gemeinsamen Kollektorwiderstand (46) gespeist werden. Die Ausgänge der beiden Eingangstransistoren sind über je einen Emitterfolger (18, 28) mit dem Ausgang der Kippschaltung verbunden. Beim Wechsel der zu speichernden Dateneingangssignale oder der Taktsignale werden hierdurch Störanteile am Ausgang der Kippschaltung, welche durch das Anschalten des einen und das Ausschalten des anderen Emitterfolger verursacht sind, kompensiert.
摘要翻译： 在一个触发器包括第一（10）和第二（12）功率分布开关噪声尖峰是在触发器的防止经由公共的集电极电阻器（46）的两个电流分布交换机的输入晶体管（32，50）供给的输出。 两个输入晶体管的输出端分别通过射极跟随器（18,28）连接到触发器电路的输出端。 当改变要存储的数据输入信号或时钟信号时，由此导致触发器输出端的噪声分量由于接通而导致，而另一个发射极跟随器的关断被补偿。
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7.发明公开TWO-TRANSISTOR SRAM SEMICONDUCTOR STRUCTURE AND METHODS OF FABRICATION 审中-公开SRAM-HALBLEITERSTRUKTUR MIT ZWEI TRANSISTOREN UND VERFAHREN ZUR HERSTELLUNG
公开(公告)号：EP3149737A4
公开(公告)日：2017-06-28
申请号：EP15844256
申请日：2015-09-25
申请人： KILOPASS TECH INC
IPC分类号： H01L27/102 , G11C11/39 , G11C11/41 , G11C11/411 , H01L21/8249 , H01L27/06 , H01L27/082 , H01L27/11
CPC分类号： H01L27/1104 , G11C11/39 , G11C11/41 , G11C11/411 , H01L21/8229 , H01L21/8249 , H01L27/0623 , H01L27/0821 , H01L27/0826 , H01L27/1025 , H01L27/1027 , H01L27/11 , H01L27/1116 , H01L29/0649 , H01L29/0804 , H01L29/083 , H01L29/0847 , H01L29/1004 , H01L29/1012 , H01L29/1095 , H01L29/66272 , H01L29/66386 , H01L29/732 , H01L29/742 , H01L29/7455
摘要： A memory cell based upon thyristors for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM. Special circuitry provides lowered power consumption during standby.
摘要翻译： 描述基于用于SRAM集成电路的晶闸管的存储器单元以及用于制造它的过程。 存储器单元可以以MOS和双极选择晶体管的不同组合来实现，或者不具有选择晶体管，其中半导体衬底中的晶闸管具有浅沟槽隔离。 标准CMOS工艺技术可用于制造SRAM。 特殊电路可在待机期间降低功耗。
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8.发明公开
公开(公告)号：EP3053166A4
公开(公告)日：2017-05-10
申请号：EP14847884
申请日：2014-09-30
IPC分类号： G11C11/39 , G11C11/411
CPC分类号： G11C11/40 , G11C7/12 , G11C11/39 , G11C11/411 , G11C2207/12
摘要： A two transistor ternary random access memory (TTTRAM) circuit includes an voltage/current input, an input/output switch, a first transistor, a first pull up resistor, a second transistor, and a second pull up resistor. The first transistor has a first emitter, a first collector connected to the input/output switch, and a first base. The first pull up resistor is connected to the first emitter and the voltage/current input. The second transistor has a second emitter connected to ground, a second collector, and a second base connected to the input/output switch. The second pull up resistor is connected to the first base, the second collector, and the voltage/current input.
摘要翻译： 双晶体管三态随机存取存储器（TTTRAM）电路包括电压/电流输入，输入/输出开关，第一晶体管，第一上拉电阻器，第二晶体管和第二上拉电阻器。 第一晶体管具有第一发射极，连接到输入/输出开关的第一集电极以及第一基极。 第一个上拉电阻连接到第一个发射极和电压/电流输入。 第二晶体管具有连接到地的第二发射极，第二集电极和连接到输入/输出开关的第二基极。 第二个上拉电阻连接到第一个基极，第二个集电极和电压/电流输入。
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9.发明公开TWO-TRANSISTOR SRAM SEMICONDUCTOR STRUCTURE AND METHODS OF FABRICATION 审中-公开SRAM-HALBLEITERSTRUKTUR MIT ZWEI TRANSISTOREN UND VERFAHREN ZUR HERSTELLUNG
公开(公告)号：EP3149737A1
公开(公告)日：2017-04-05
申请号：EP15844256.6
申请日：2015-09-25
IPC分类号： G11C11/00 , G11C11/411 , G11C11/419 , G11C11/34 , G11C7/12
CPC分类号： H01L27/1104 , G11C11/39 , G11C11/41 , G11C11/411 , H01L21/8229 , H01L21/8249 , H01L27/0623 , H01L27/0821 , H01L27/0826 , H01L27/1025 , H01L27/1027 , H01L27/11 , H01L27/1116 , H01L29/0649 , H01L29/0804 , H01L29/083 , H01L29/0847 , H01L29/1004 , H01L29/1012 , H01L29/1095 , H01L29/66272 , H01L29/66386 , H01L29/732 , H01L29/742 , H01L29/7455
摘要： A memory cell based upon thyristors for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM. Special circuitry provides lowered power consumption during standby.
摘要翻译： 基于用于SRAM集成电路的晶闸管的存储单元与其制造方法一起被描述。 存储器单元可以以具有浅沟槽隔离的半导体衬底中的晶闸管与MOS和双极选择晶体管的不同组合或不具有选择晶体管来实现。 标准CMOS工艺技术可用于制造SRAM。 特殊电路在待机期间提供降低的功耗。
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公开(公告)号：EP0031036A2
公开(公告)日：1981-07-01
申请号：EP80107218.2
申请日：1980-11-20
CPC分类号： G11C11/411 , G11C11/403 , G11C11/4067
摘要： This describes a sense latch for a bipolar dynamic array in which each cell is comprised of a capacitor (CS) and a pnp-npn transistor. Cell information is stored in the capacitor (CS). The capacitor may be either a discreet capacitor or may be formed as part of the base node of the pnp transistor. The sense latch (12) of the invention comprises a pair of cross coupled transistors (40,41) coupled between a pair of capacitively loaded bit lines (10,11) of the array with one of the bit lines (10,11) being coupled to a data cell (15,16) and the other being coupled to a reference cell (13,14). Means for precharging the bit lines (10,11) to a fixed voltage level and means for reading the cell to charge one of the bit lines to a level greater than the precharge level and apply a differential signal to the latch (12) are also provided so that during the reading cycle one of the transistors (40,41) in the latch becomes turned on so that the voltage levels of both bit lines (10,11) are determined by the characteristics of the turned on transistor (40,41) only. The voltage on one line is determined by the forward base-emitter characteristics of the turned on transistor and the voltage on the other line is determined by the saturated collector-emitter I characteristics of the same turned on transistor.
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