公开(公告)号：EP0419066A2

公开(公告)日：1991-03-27

申请号：EP90309468.8

申请日：1990-08-30

申请人： International Business Machines Corporation

发明人： Bonevento, Francis Michael ,  McGovern, Joseph Patrick ,  Thomas, Eugene Mitchell

IPC分类号： G06F15/16 ,  G06F13/42 ,  G06F9/46

CPC分类号： G06F9/3869 ,  G06F5/06 ,  G06F13/4226 ,  G06F2205/064

摘要： A microprocessor system which includes a processor unit with system memory and a separate buffer memory, one or more subsystem adapter units with memory, optional I/O devices which may attach to the adapters, and a bus interface. The memory in the processor and the memory in the adapters are used by the system as a shared memory (106,112) which is configured as a distributed FIFO circular queue (a pipe). Unit to unit asynchronous communication is accomplished by placing control elements (104,116) on the pipe which represent requests, replies, and status information. The units (622,624) send and receive control elements (104,116) independent of the other units which allows free flowing asynchronous delivery of control information and data between units (622,624). The shared memory (106,112) can be organised as pipe pairs between each pair of units to allow full duplex operation by using one pipe for outbound control elements (104,116) and the other pipe for inbound control elements (104,116). The control elements (104,116) have standard fixed header fields with variable fields following the fixed header. The fixed header allows a common interface protocol to be used by different hardware adapters. The combination of the pipe and the common interface protocol allows many different types of hardware adapters to asynchronously communicate, resulting in higher overall throughput due to lower interrupt overhead.

摘要翻译： 一种微处理器系统，包括与系统存储器和一个单独的缓冲存储器，一个或多个子系统适配器单元与存储器，其可以附连到适配器可选I / O设备，以及总线接口的处理器单元。 在处理器中的存储器，并在适配器存储器中的系统所使用作为被配置为分布式FIFO循环队列（配管）的共享存储器（106.112）所有。 单元到单元的异步通信通过将在管控制元件（104.116），其代表请求，应答和状态信息来实现的。 作为单元（622.624）发送和接收（104.116）独立，其允许控制信息和数据单元之间自由流动的异步传送（622.624）的其它单元的控制元件。 共享存储器（106.112）可以被组织成各对单元之间配管对以允许全双工操作，通过使用一个管用于出站控制元件（104.116）和其他管的入站控制元件（104.116）。 所述控制元件（104.116）具有可变域标准的固定头字段继固定报头。 所述固定报头允许通过不同的硬件适配器一起使用的通用接口协议。 管和共用接口协议的组合允许许多不同类型的硬件适配器的异步通信，在更高的总吞吐量所得由于较低的中断开销。

公开(公告)号：EP0419066A3

公开(公告)日：1994-04-20

申请号：EP90309468.8

申请日：1990-08-30

申请人： International Business Machines Corporation

发明人： Bonevento, Francis Michael ,  McGovern, Joseph Patrick ,  Thomas, Eugene Mitchell

IPC分类号： G06F15/16 ,  G06F13/42 ,  G06F9/46

CPC分类号： G06F9/3869 ,  G06F5/06 ,  G06F13/4226 ,  G06F2205/064

摘要： A microprocessor system which includes a processor unit with system memory and a separate buffer memory, one or more subsystem adapter units with memory, optional I/O devices which may attach to the adapters, and a bus interface. The memory in the processor and the memory in the adapters are used by the system as a shared memory (106,112) which is configured as a distributed FIFO circular queue (a pipe). Unit to unit asynchronous communication is accomplished by placing control elements (104,116) on the pipe which represent requests, replies, and status information. The units (622,624) send and receive control elements (104,116) independent of the other units which allows free flowing asynchronous delivery of control information and data between units (622,624). The shared memory (106,112) can be organised as pipe pairs between each pair of units to allow full duplex operation by using one pipe for outbound control elements (104,116) and the other pipe for inbound control elements (104,116). The control elements (104,116) have standard fixed header fields with variable fields following the fixed header. The fixed header allows a common interface protocol to be used by different hardware adapters. The combination of the pipe and the common interface protocol allows many different types of hardware adapters to asynchronously communicate, resulting in higher overall throughput due to lower interrupt overhead.

摘要翻译： 一种微处理器系统，其包括具有系统存储器和单独缓冲存储器的处理器单元，具有存储器的一个或多个子系统适配器单元，可以连接到适配器的可选I / O设备以及总线接口。 处理器中的存储器和适配器中的存储器被系统用作配置为分布式FIFO循环队列（管道）的共享存储器（106,112）。 单元到单元的异步通信是通过在代表请求，回复和状态信息的管道上放置控制元件（104,116）来完成的。 单元（622,624）独立于其他单元发送和接收控制元素（104,116），这允许单元（622,624）之间自由流动的控制信息和数据的异步传送。 共享存储器（106,112）可以被组织为每对单元之间的管道对，以允许通过使用一个管道用于出站控制元件（104,116）而另一个管道用于入站控制元件（104,116）来允许全双工操作。 控制元素（104,116）具有标准的固定标题字段，其具有跟随固定标题的可变字段。 固定头允许不同的硬件适配器使用通用接口协议。 管道和通用接口协议的组合允许许多不同类型的硬件适配器进行异步通信，由于较低的中断开销，因此可以提高整体吞吐量。