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    UTILIZING PIPELINE REGISTERS AS INTERMEDIATE STORAGE
    2.
    发明公开
    UTILIZING PIPELINE REGISTERS AS INTERMEDIATE STORAGE 审中-公开
    VERWENDUNG VON PIPELINERISISN ALS ZWISCHENSPEICHER

    公开(公告)号：EP3143495A1

    公开(公告)日：2017-03-22

    申请号：EP15724805.5

    申请日：2015-04-21

    申请人： Qualcomm Incorporated

    发明人： CHEN, Lin ,  DU, Yun ,  UDAYAKUMARAN, Sumesh ,  ZHANG, Chihong ,  GRUBER, Andrew Evan

    IPC分类号： G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/3012 ,  G06F9/30032 ,  G06F9/3017 ,  G06F9/3869 ,  G06F9/3875

    摘要： In one example, a method includes responsive to receiving, by a processing unit, one or more instructions requesting that a first value be moved from a first general purpose register (GPR) to a third GPR and that a second value be moved from a second GPR to a fourth GPR, copying, by an initial logic unit and during a first clock cycle, the first value to an initial pipeline register, copying, by the initial logic and during a second clock cycle, the second value to the initial pipeline register, copying, by a final logic unit and during a third clock cycle, the first value from a final pipeline register to the third GPR, and copying, by the final logic unit and during a fourth clock cycle, the second value from the final pipeline register to the fourth GPR.

    摘要翻译： 在一个示例中，一种方法包括响应于由处理单元接收请求将第一值从第一通用寄存器（GPR）移动到第三GPR的一个或多个指令，并且第二值从第二个 GPR到第四个GPR，由初始逻辑单元和在第一时钟周期期间将第一个值复制到初始流水线寄存器，通过初始逻辑复制第二个时钟周期，将第二个值复制到初始流水线寄存器 ，由最终逻辑单元和在第三时钟周期期间将第一值从最终流水线寄存器复制到第三GPR，并且由最终逻辑单元和在第四时钟周期期间复制来自最终流水线的第二值 注册到第四个GPR。

    PIPELINED CONFIGURABLE PROCESSOR
    3.
    发明公开
    PIPELINED CONFIGURABLE PROCESSOR 审中-公开
    可配置的流水线处理器

    公开(公告)号：EP3063651A1

    公开(公告)日：2016-09-07

    申请号：EP14796852.3

    申请日：2014-10-28

    申请人： Silicon Tailor Limited

    发明人： METZGEN, Paul

    IPC分类号： G06F15/78 ,  G06F9/38

    CPC分类号： G06F15/7867 ,  G06F1/10 ,  G06F9/3851 ,  G06F9/3869 ,  G06F9/3873 ,  G06F9/3897 ,  G06F15/7878

    摘要： A configurable processing circuit capable of handling multiple threads simultaneously, the circuit comprising a thread data store, a plurality of configurable execution units, a configurable routing network for connecting locations in the thread data store to the execution units, a configuration data store for storing configuration instances that each define a configuration of the routing network and a configuration of one or more of the plurality of execution units, and a pipeline formed from the execution units, the routing network and the thread data store that comprises a plurality of pipeline sections configured such that each thread propagates from one pipeline section to the next at each clock cycle, the circuit being configured to: (i) associate each thread with a configuration instance; and (ii) configure each of the plurality of pipeline sections for each clock cycle to be in accordance with the configuration instance associated with the respective thread that will propagate through that pipeline section during the clock cycle.

    IDLE-ELEMENT PREDICTION CIRCUITRY AND ANTI-THRASHING LOGIC
    5.
    发明公开
    IDLE-ELEMENT PREDICTION CIRCUITRY AND ANTI-THRASHING LOGIC 有权
    SCHALTKREIS ZUR VORHERSAGE LEERLAUFENDER ELEMENTE UND ANTI-ÜBERLASTUNGSLOGIK

    公开(公告)号：EP2930590A1

    公开(公告)日：2015-10-14

    申请号：EP15162985.4

    申请日：2006-05-08

    申请人： Qualcomm Incorporated

    发明人： Dockser, Kenneth Alan

    IPC分类号： G06F1/32 ,  G06F9/38

    CPC分类号： G06F1/3287 ,  G06F1/3228 ,  G06F9/3869 ,  Y02D10/171 ,  Y02D50/20

    摘要： Control logic (45) monitors use of a particular functional unit (21) (e.g., a divider, or multiplier or the like) in a programmable processor (10), and the control logic (45) powers the functional unit down when it has not been used for a specified time period. A counter (31) (local or central) and time threshold determine when the period has elapsed without use of the functional unit. The control logic (45) also monitors how soon the functional unit (21) is woken up again, to determine if power control is causing thrashing. Upon the determination of such thrashing, the unit automatically adjusts its threshold period, to minimize thrashing. In an example of the control logic, when it determines that it is being too conservative, it lowers the threshold. Mode bits may allow the programmer to override the power-down logic to either keep the logic always powered-up, or always powered-down.

    摘要翻译： 控制逻辑（45）监视可编程处理器（10）中特定功能单元（21）（例如，分频器或乘法器等）的使用，并且当控制逻辑（45）具有 未在特定时间段内使用。 计数器（31）（本地或中央）和时间阈值确定何时已经过去，而不使用功能单元。 控制逻辑（45）还监视功能单元（21）再次被唤醒的时间，以确定功率控制是否引起颠簸。 在确定这种颠簸后，本机自动调整其阈值周期，以最大限度地减少抖动。 在控制逻辑的一个例子中，当它确定它太保守时，它会降低阈值。 模式位可能允许程序员覆盖掉电逻辑，以使逻辑总是上电，或者总是断电。

    Method and apparatus to control current transients in a processor
    6.
    发明公开
    Method and apparatus to control current transients in a processor 审中-公开
    用于控制处理器中的电流瞬变的方法和设备

    公开(公告)号：EP2808756A1

    公开(公告)日：2014-12-03

    申请号：EP14163762.9

    申请日：2014-04-07

    申请人： Intel Corporation

    发明人： Rosenzweig, Nir ,  Sperber, Zeev ,  Rotem, Efraim

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3206 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/3836 ,  G06F9/3869 ,  Y02D10/126 ,  Y02D10/172

    摘要： In an embodiment, a processor includes at least one core. The at least one core includes an execution unit and a current protection (IccP) controller. The IccP controller may receive instruction width information associated with one or more instructions of an instruction queue prior to execution of the instructions by the execution unit. The IccP controller may determine an anticipated highest current level (Icc) for the at least one core based on the instruction width information. The IccP controller may generate a request for a first license for the at least one core that is associated with the Icc. Other embodiments are described and claimed.

    摘要翻译： ，实施例中的处理器包括至少一个芯。 所述至少一个芯包括在执行单元和电流保护（ICCP）控制器。 政府间委员会控制器可接收与由所述执行单元执行所述指令之前的指令队列的一个或多个指令相关联的指令宽度的信息。 政府间委员会控制器可以在预期的最高电流电平（ICC）确定性矿用于基于所述指令的所述至少一个芯体宽度的信息。 政府间委员会控制器可以产生用于所述至少一个芯部的第一许可证的请求没有与所述ICC相关联。 其他实施例中描述并要求保护。

    A clock control circuit and method
    7.
    发明公开
    A clock control circuit and method 有权
    Taktsteuerschaltung und -verfahren

    公开(公告)号：EP2796958A1

    公开(公告)日：2014-10-29

    申请号：EP13164744.8

    申请日：2013-04-22

    申请人： NXP B.V.

    发明人： Hoogerbrugge, Jan ,  Guntur, Surendra ,  Al-Kadi, Ghiath ,  Meijer, Rinze ,  Fatemi, Hamed

    IPC分类号： G06F1/04

    CPC分类号： G06F1/06 ,  G06F1/04 ,  G06F1/08 ,  G06F9/38 ,  G06F9/3869 ,  G06F11/00

    摘要： This invention provides a clock control circuit, which can be added to any pipeline-processor to solve timing problems arising from variations due to process outcome and environmental conditions. Critical instructions are detected (instructions that exercise critical paths) in conjunction with environmental sensing (such as process, temperature and voltage). This information is used to control cycle stealing.

    摘要翻译： 本发明提供一种时钟控制电路，其可以被添加到任何流水线处理器以解决由于过程结果和环境条件引起的变化引起的定时问题。 检测到关键指令（执行关键路径的指令）与环境感测（如过程，温度和电压）相结合。 此信息用于控制周期窃取。

    Processor, information processing apparatus, and power consumption management method
    8.
    发明公开
    Processor, information processing apparatus, and power consumption management method 审中-公开
    信息技术研究所助理教授和Verfahren zur Verwaltung des Leistungsverbrauchs

    公开(公告)号：EP2703944A2

    公开(公告)日：2014-03-05

    申请号：EP13181734.8

    申请日：2013-08-26

    申请人： FUJITSU LIMITED

    发明人： Koinuma, Hideyuki ,  Fukumura, Hiromi ,  Hara, Michiharu ,  Kageyama, Hironobu ,  Yoshida, Toshio

    IPC分类号： G06F1/32 ,  G06F1/28

    CPC分类号： G06F1/324 ,  G06F1/28 ,  G06F1/3206 ,  G06F9/3836 ,  G06F9/3869 ,  Y02D10/126 ,  Y02D50/20

    摘要： When a result of detection by a current sensor 22 represents the occurrence of an overcurrent, comparators 23 of PSUs 2 transmit a present report indicating that fact to an SP 1. Receiving the present report, an FPGA 12 of the SP 1 turns on a forcible low-power signal. A forcible power saving control circuit 32 of a CPU 3 directly inputs a forcible-low-power-mode signal, turns on the signal, and controls an instruction issuance control unit that is configured to issue an instruction in the CPU 3, so as to immediately decrease the frequency at which the instruction issuance control unit issues instructions. This control is cancelled after the DVFS control circuit 35 has reduced the voltage of power output from a DDC 4 and a clock frequency output from a PLL circuit.

    摘要翻译： 当电流传感器22的检测结果表示过电流的发生时，PSU的比较器23向SP 1发送指示该事实的当前报告。接收到本报告，SP1的FPGA12接通强制 低功率信号。 CPU3的强制省电控制电路32直接输入强制低功率模式信号，接通信号，并且控制配置为在CPU 3中发出指令的指令发布控制单元，以便 立即降低指令发布控制单元发出指令的频率。 在DVFS控制电路35降低从DDC 4输出的电力电压和从PLL电路输出的时钟频率之后，该控制被取消。

    SINGLE CYCLE MULTI-BRANCH PREDICTION INCLUDING SHADOW CACHE FOR EARLY FAR BRANCH PREDICTION
    9.
    发明公开
    SINGLE CYCLE MULTI-BRANCH PREDICTION INCLUDING SHADOW CACHE FOR EARLY FAR BRANCH PREDICTION 有权
    使用延迟CACHE早期和远端结预测多支单曲循环预测

    公开(公告)号：EP2616928A4

    公开(公告)日：2014-02-26

    申请号：EP11826042

    申请日：2011-09-16

    申请人： SOFT MACHINES INC

    发明人： ABDALLAH MOHAMMAD

    IPC分类号： G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/3806 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30047 ,  G06F9/3804 ,  G06F9/3836 ,  G06F9/3844 ,  G06F9/3869 ,  G06F12/0875 ,  G06F2212/1016 ,  G06F2212/452

    摘要： A method of identifying instructions including accessing a plurality of instructions that comprise multiple branch instructions. For each branch instruction of the multiple branch instructions, a respective first mask is generated representing instructions that are executed if a branch is taken. A respective second mask is generated representing instructions that are executed if the branch is not taken. A prediction output is received that comprises a respective branch prediction for each branch instruction. For each branch instruction, the prediction output is used to select a respective resultant mask from among the respective first and second masks. For each branch instruction, a resultant mask of a subsequent branch is invalidated if a previous branch is predicted to branch over said subsequent branch. A logical operation is performed on all resultant masks to produce a final mask. The final mask is used to select a subset of instructions for execution.