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1.发明公开Method and apparatus for fetching instructions 有权Verfahren und Vorrichtung zum Abrufen von Befehlen
公开(公告)号：EP0945785A2
公开(公告)日：1999-09-29
申请号：EP99301454.7
申请日：1999-02-26
CPC分类号： G06F9/3804 , G06F9/322
摘要： A processor and method of fetching an instruction from a memory are disclosed. According to the method of the present invention, a plurality of target addresses are determined utilizing a plurality of previously fetched instructions, and a sequential address is determined utilizing a last of the plurality of previously fetched instructions. Concurrently with the determination of the target addresses and the sequential address, a select signal specifying one of the plurality of target addresses or the sequential address is generated. The select signal is used to select one of the plurality of target addresses or the sequential address as a memory request address. The memory request address is then transmitted from the processor to the memory so that the memory will supply at least one instruction to the processor. By generating the target addresses and sequential address concurrently with the generation of the selection signal, instruction fetch latency is reduced.
摘要翻译： 公开了一种从存储器取出指令的处理器和方法。 根据本发明的方法，利用多个先前获取的指令来确定多个目标地址，并且利用多个先前获取的指令中的最后一个来确定顺序地址。 同时确定目标地址和顺序地址，产生指定多个目标地址之一或顺序地址的选择信号。 选择信号用于选择多个目标地址之一或顺序地址作为存储器请求地址。 然后，存储器请求地址从处理器发送到存储器，使得存储器将向处理器提供至少一个指令。 通过产生选择信号同时产生目标地址和顺序地址，减少指令提取延迟。
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公开(公告)号：EP0945785B1
公开(公告)日：2008-06-18
申请号：EP99301454.7
申请日：1999-02-26
CPC分类号： G06F9/3804 , G06F9/322
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公开(公告)号：EP0945785A3
公开(公告)日：2000-09-27
申请号：EP99301454.7
申请日：1999-02-26
CPC分类号： G06F9/3804 , G06F9/322
摘要： A processor and method of fetching an instruction from a memory are disclosed. According to the method of the present invention, a plurality of target addresses are determined utilizing a plurality of previously fetched instructions, and a sequential address is determined utilizing a last of the plurality of previously fetched instructions. Concurrently with the determination of the target addresses and the sequential address, a select signal specifying one of the plurality of target addresses or the sequential address is generated. The select signal is used to select one of the plurality of target addresses or the sequential address as a memory request address. The memory request address is then transmitted from the processor to the memory so that the memory will supply at least one instruction to the processor. By generating the target addresses and sequential address concurrently with the generation of the selection signal, instruction fetch latency is reduced.
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