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1.发明公开An asymmetric multilayered dielectric material and a flash EEPROM using the same 失效不对称merhschichtiges介电材料和一个包含它的闪速EEPROM。
公开(公告)号：EP0574671A3
公开(公告)日：1994-10-12
申请号：EP93106488.5
申请日：1993-04-21
IPC分类号： H01L29/62 , H01L29/788 , H01L27/115
CPC分类号： H01L29/513 , H01L27/115 , H01L29/7883
摘要： A flash EEPROM is produced comprising multiple MOS cells. In each cell, programming and erasing are performed through tunneling from the write gate (22) to the floating gate (14) and by tunneling from the floating gate to the erase gate (10), respectively. The directional dielectric employed is a multilayered structured (MLS) oxide (16), where thin oxide and thin polycrystalline silicon form alternating layers. The layering is asymmetric: that is, either the uppermost or bottommost layer is thicker than the other layers. As a result of this structure, the oxide exhibits directionality, that is, the tunneling is easier in one direction than the reverse direction, and significantly enhances the tunneling phenomena (tunneling current can be observed at as low as 4.7V). In addition, the MLS oxide can be fabricated having different dielectric constants. The directionality, coupled with the separate write and erase gates, gives the new flash EEPROM cell a number of advantages: it is low-voltage operable, it is highly resistant to disturbance and has an easily scalable structure (that is, it can be made to operate at any given voltage within a specified scale).
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2.发明公开Sensing circuit for semiconductor memory with limited bitline voltage swing 失效用于具有双线电压摆幅的半导体存储器的感应电路
公开(公告)号：EP0558970A3
公开(公告)日：1994-06-01
申请号：EP93102132.3
申请日：1993-02-11
IPC分类号： G11C11/409 , G11C7/06
CPC分类号： G11C11/4091 , G11C7/065
摘要： A sensing circuit for dynamic random access memory is disclosed including a pair of bitlines precharged to a first voltage before sensing. A sense amplifier circuit is provided having one node thereof being connected to an external power supply via a switching means including pulsed sense clocks. Control means is provided and is connected to the switching means for controlling the switching means such that the voltage of the power supply is coupled to the node of the sense amplifier for activation for a predetermined period of time, thereby limiting the swing for the high-going bitline to a second voltage lower than said power supply voltage and higher than said first voltage. The reduced bitline swings are achieved by means of the pulsed sense clocks and the pulse widths for sense clocks are determined by means of a reference bitlines connected to the control means.
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3.发明公开Variable bitline precharge voltage sensing technique for DRAM structures 失效Spannungsabfühlverfahrendurch variabele BitleitungsvorladungfürDRAM Strukturen。
公开(公告)号：EP0595747A2
公开(公告)日：1994-05-04
申请号：EP93480137.4
申请日：1993-09-21
发明人： Dhong, Sang Hoo , Shin,Hyun Jong , Taira, Yoichi , Kirihata, Toshiaki , Sunaga, Toshio , Terman, Lewis Madison
IPC分类号： G11C11/409
CPC分类号： G11C11/4094
摘要： A sensing technique uses a variable precharge voltage sensing with a single bitline swing in a DRAM cell or array of DRAM cells so that the power dissipation is reduced. The bitline precharge voltage varies from one RAS cycle to the next RAS cycle depending upon the level of the data in the accessed cells. Such an arrangement eliminates the need for a reference voltage generator since the precharge voltage is not the same voltage for each RAS cycle.
摘要翻译： 感测技术在DRAM单元或DRAM单元阵列中使用单个位线摆动的可变预充电电压感测，从而降低功耗。 位线预充电电压根据所访问单元中数据的电平而从RAS周期到下一个RAS周期不等。 这种布置消除了对参考电压发生器的需要，因为每个RAS周期的预充电电压不是相同的电压。
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4.发明公开Structure and fabrication method for a double trench memory cell device 失效Struktur und Herstellungsverfahrenfürein Doppelgraben-Speicherzellen-Bauteil。
公开(公告)号：EP0463389A1
公开(公告)日：1992-01-02
申请号：EP91108661.9
申请日：1991-05-28
发明人： Dhong, Sang Hoo , Hwang, Wei
IPC分类号： H01L27/08 , H01L27/108
CPC分类号： H01L27/10841 , H01L29/945
摘要： A method is described for fabricating a novel double trench memory structure including a shallow trench (15) access transistor adjacent to a deep trench (11) storage capacitor. The described three-dimensional DRAM cell structure consists of shallow trench access transistors and deep trench storage capacitors in a n-well (12) disposed on a semiconductor substrate (10). In the fabrication method, the vertical access transistors are built adjacent to the one side of one deep substrate-plate trench storage capacitor. The vertical access transistor partially overlaps the storage capacitor. An asymmetric insulation scheme (34) decreases the overlap capacitance between word line (20) and storage node (30). The contact between drain region (26) and storage node (30) is made by selectively powing an epitaxial layer after forming the shallow trench (15). Arrangement of the access transistors and trench storage capacitor are different from that of standard single trench cells. The structure may be fabricated for p-channel or n-channel embodiments.
摘要翻译： 描述了一种用于制造包括与深沟槽（11）存储电容器相邻的浅沟槽（15）存取晶体管的新型双沟槽存储器结构的方法。 所描述的三维DRAM单元结构由设置在半导体衬底（10）上的n阱（12）中的浅沟槽存取晶体管和深沟槽存储电容器组成。 在制造方法中，垂直存取晶体管被构建为与一个深衬底 - 平板沟槽存储电容器的一侧相邻。 垂直存取晶体管部分地与存储电容器重叠。 不对称绝缘方案（34）减小字线（20）和存储节点（30）之间的重叠电容。 在形成浅沟槽（15）之后，通过选择性地对外延层进行功率来制造漏区（26）和存储节点（30）之间的接触。 存取晶体管和沟槽存储电容器的布置与标准单沟槽电池的布置不同。 该结构可以用于p沟道或n沟道实施例。
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公开(公告)号：EP0493659B1
公开(公告)日：1997-05-28
申请号：EP91118320.0
申请日：1991-10-28
发明人： Dhong, Sang Hoo , Hwang, Wei , Taira, Yoichi
IPC分类号： G11C11/408 , G11C8/00
CPC分类号： H03K5/023 , G11C11/4085
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6.发明公开
公开(公告)号：EP0595747A3
公开(公告)日：1995-04-26
申请号：EP93480137.4
申请日：1993-09-21
发明人： Dhong, Sang Hoo , Shin,Hyun Jong , Taira, Yoichi , Kirihata, Toshiaki , Sunaga, Toshio , Terman, Lewis Madison
IPC分类号： G11C11/409
CPC分类号： G11C11/4094
摘要： A sensing technique uses a variable precharge voltage sensing with a single bitline swing in a DRAM cell or array of DRAM cells so that the power dissipation is reduced. The bitline precharge voltage varies from one RAS cycle to the next RAS cycle depending upon the level of the data in the accessed cells. Such an arrangement eliminates the need for a reference voltage generator since the precharge voltage is not the same voltage for each RAS cycle.
摘要翻译： 感测技术在DRAM单元或DRAM单元阵列中使用具有单个位线摆动的可变预充电电压感测，从而降低功耗。 位线预充电电压从一个RAS周期变化到下一个RAS周期，这取决于所访问的单元中的数据的电平。 这样的布置消除了对参考电压发生器的需要，因为预充电电压对于每个RAS周期不是相同的电压。
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公开(公告)号：EP0377827B1
公开(公告)日：1995-03-08
申请号：EP89122625.0
申请日：1989-12-08
IPC分类号： G11C8/00 , G11C7/00 , H03K17/693
摘要： A boost clock signal generator which provides a boost clock signal from a pair of phase clocks. A pair of differentially-connected FET transistors (46) which generate a boost clock signal. The transistors have drain connections connected to each of two clock signals, and commonly connected sources which form an output terminal for the boost clock signal. A series pass FET transistor (58, 59) is connected with each gate of the differential transistors for maintaining the gate at a floating voltage potential. A pair of capacitive elements couple the drain of each pair of differentially-connected FET transistors to the gate of an opposite transistor. A first and second logic circuit (78, 79) are connected to the series pass FET transistors for enabling one or the other of the differentially-connected FET transistors into conduction. The pair of capacitive coupling elements (51, 52) coupling the drain of each pair of differentially-connected FET transistors to the gate of an opposite transistor increase switching speed of the clock signal generator.
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8.发明公开Sensing circuit for semiconductor memory with limited bitline voltage swing 失效DetektierschaltungfürHalbleiterspeicher mitbeschränktemBitleitungsspannungshub。
公开(公告)号：EP0558970A2
公开(公告)日：1993-09-08
申请号：EP93102132.3
申请日：1993-02-11
IPC分类号： G11C11/409 , G11C7/06
CPC分类号： G11C11/4091 , G11C7/065
摘要： A sensing circuit for dynamic random access memory is disclosed including a pair of bitlines precharged to a first voltage before sensing. A sense amplifier circuit is provided having one node thereof being connected to an external power supply via a switching means including pulsed sense clocks. Control means is provided and is connected to the switching means for controlling the switching means such that the voltage of the power supply is coupled to the node of the sense amplifier for activation for a predetermined period of time, thereby limiting the swing for the high-going bitline to a second voltage lower than said power supply voltage and higher than said first voltage. The reduced bitline swings are achieved by means of the pulsed sense clocks and the pulse widths for sense clocks are determined by means of a reference bitlines connected to the control means.
摘要翻译： 公开了一种用于动态随机存取存储器的感测电路，包括在感测之前预充电到第一电压的一对位线。 提供了一种读出放大器电路，其一个节点通过包括脉冲读出时钟的开关装置连接到外部电源。 提供控制装置并且连接到开关装置，用于控制开关装置，使得电源的电压耦合到读出放大器的节点，以激活预定的时间段，从而限制高电平的摆动， 位于低于所述电源电压并高于所述第一电压的第二电压。 通过脉冲感测时钟来实现减小的位线摆动，并且通过连接到控制装置的参考位线来确定感测时钟的脉冲宽度。
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9.发明公开
公开(公告)号：EP0431290A3
公开(公告)日：1992-01-29
申请号：EP90120140.0
申请日：1990-10-20
IPC分类号： H03K17/56 , H03K19/094
CPC分类号： H01L27/0711
摘要： Circuitry for implementing a gate enhanced lateral transistor (3l) to provide a circuit having a bipolar current driving capability and an FET channel voltage drop. The circuits provide switching of the lateral transistor by enabling both gate and base connections. The device is merged into an FET providing essentially no voltage drop across the collector-emitter connections permitting the collector to reach a full power supply voltage.
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公开(公告)号：EP0377827A3
公开(公告)日：1991-07-31
申请号：EP89122625.0
申请日：1989-12-08
IPC分类号： G11C8/00 , G11C7/00 , H03K17/693
摘要： A boost clock signal generator which provides a boost clock signal from a pair of phase clocks. A pair of differentially-connected FET transistors (46) which generate a boost clock signal. The transistors have drain connections connected to each of two clock signals, and commonly connected sources which form an output terminal for the boost clock signal. A series pass FET transistor (58, 59) is connected with each gate of the differential transistors for maintaining the gate at a floating voltage potential. A pair of capacitive elements couple the drain of each pair of differentially-connected FET transistors to the gate of an opposite transistor. A first and second logic circuit (78, 79) are connected to the series pass FET transistors for enabling one or the other of the differentially-connected FET transistors into conduction. The pair of capacitive coupling elements (51, 52) coupling the drain of each pair of differentially-connected FET transistors to the gate of an opposite transistor increase switching speed of the clock signal generator.
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