公开(公告)号：EP0481233A3

公开(公告)日：1992-04-29

申请号：EP91115825.1

申请日：1991-09-18

申请人： International Business Machines Corporation

发明人： So, Kimming ,  Wang, Wen-Hann

IPC分类号： G06F12/08

CPC分类号： G06F12/0811 ,  G06F12/0822 ,  G06F12/084

摘要： A system and method is disclosed for a multiprocessor system (MP) having multiple levels of cache storage and shared memory. A multiprocessor system (MP) is disclosed which comprises microprocessors (MPU). The MPUs, which have on-chip L₁ caches, are interfaced with external L₂ caches. D₂ directories are situated parallel to the L₂ caches and shadow the L₁ caches. The D₂ directories maintain data coherence among all the caches and a main memory, while decreasing the amount of interference with the on-chip L₁ caches. Reducing the amount of interference with the on-chip L₁ caches. Reducing the amount of interference permits the MPUs to perform at higher speeds and permits the further coupling of additional MPUs to the multiprocessor system (MP).

公开(公告)号：EP0649094A1

公开(公告)日：1995-04-19

申请号：EP94306672.0

申请日：1994-09-12

申请人： International Business Machines Corporation

发明人： So Kimming ,  Wang, Wen-Hann

IPC分类号： G06F12/08

CPC分类号： G06F12/0811

摘要： A system and method for managing caches in a multiprocessor having multiple levels of caches. An inclusion architecture and procedure are defined through which the L2 caches shield the L1 caches from extraneous communication at the L2, such as main memory and I/O read/write operations. Essential inclusion eliminates special communication from the L1 cache to the L2, yet maintains adequate knowledge at the L2, regarding the contents of the L1, to minimize L1 invalidations. Processor performance is improved by the reduced communication and the decreased number of invalidations. The processors and L1 caches practice a store-in policy. The L2 cache uses inclusion bits to designate by cache line a relationship between the line of data in the L2 cache and the corresponding lines as they exist in the associated L1 caches. Communication and invalidations are reduced through a selective setting/resetting of the inclusion bits and related L2 interrogation practice.

摘要翻译： 一种用于管理具有多级高速缓存的多处理器中的高速缓存的系统和方法。 定义了包含体系结构和过程，L2高速缓存通过L2高速缓存来保护L2高速缓存，例如主存储器和I / O读/写操作。 基本包含消除了从L1缓存到L2的特殊通信，但是在L2上保持足够的知识，关于L1的内容，以最小化L1无效。 通过减少的通信和减少的无效数量来改善处理器的性能。 处理器和L1缓存实践存储策略。 L2缓存使用包含比特来由缓存线指定L2高速缓存中的数据行与相关联的L1高速缓存中存在的对应行之间的关系。 通过选择性设置/重置包含位和相关的L2询问实践来减少通信和无效。

公开(公告)号：EP0481233A2

公开(公告)日：1992-04-22

申请号：EP91115825.1

申请日：1991-09-18

申请人： International Business Machines Corporation

发明人： So, Kimming ,  Wang, Wen-Hann

IPC分类号： G06F12/08

CPC分类号： G06F12/0811 ,  G06F12/0822 ,  G06F12/084

摘要： A system and method is disclosed for a multiprocessor system (MP) having multiple levels of cache storage and shared memory. A multiprocessor system (MP) is disclosed which comprises microprocessors (MPU). The MPUs, which have on-chip L₁ caches, are interfaced with external L₂ caches. D₂ directories are situated parallel to the L₂ caches and shadow the L₁ caches. The D₂ directories maintain data coherence among all the caches and a main memory, while decreasing the amount of interference with the on-chip L₁ caches. Reducing the amount of interference with the on-chip L₁ caches. Reducing the amount of interference permits the MPUs to perform at higher speeds and permits the further coupling of additional MPUs to the multiprocessor system (MP).

摘要翻译： 公开了一种具有多级缓存存储器和共享存储器的多处理器系统（MP）的系统和方法。 公开了一种包括微处理器（MPU）的多处理器系统（MP）。 具有片上L1高速缓存的MPU与外部L2高速缓存接口。 D2目录与L2高速缓存并行，并影响L1高速缓存。 D2目录保持所有高速缓存和主存储器之间的数据一致性，同时减少与片上L1高速缓存的干扰量。 降低与片上L1高速缓存的干扰量。 减少干扰量允许MPU以更高的速度执行，并允许将额外的MPU进一步耦合到多处理器系统（MP）。