-
-
公开(公告)号：EP3182415A4
公开(公告)日：2018-03-14
申请号：EP14899852
申请日：2014-08-14
发明人： KASHIHARA YOJI
CPC分类号： G11C16/24 , G11C16/0425 , G11C16/08 , G11C16/14 , G11C16/3427
摘要： A semiconductor device includes a first memory mat (1L) including a plurality of split type memory cells (250L), a second memory mat (1R) including a plurality of split type memory cells (250R), a first control gate line (CGL) connected to a control gate (CG) of a split type memory cell (100L), and a second control gate line (CGR) connected to a control gate (CG) of a split type memory cell (100R). The semiconductor device further includes a first memory gate line (MGL) connected to a memory gate (MG) of the split type memory cell (100L), and a second memory gate line (MGR) connected to a memory gate (MG) of the split type memory cell (100R).
-
公开(公告)号：EP3248194A1
公开(公告)日：2017-11-29
申请号：EP15805085.6
申请日：2015-11-25
CPC分类号： G11C16/14 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3431 , G11C16/349 , G11C2211/5648 , G11C2216/24
摘要： A non-volatile memory system utilizes partial block erasing during program operations to mitigate the effects of programming pass voltage disturbances. A programming request is received that is associated with a group of word lines from a block, such as all or a portion of the word lines. The system erases and soft programs the block prior to beginning programming. The system programs a subset of the word lines of the block for the programming request. After programming the subset of word lines, the system pauses the programming operation and performs an erase operation for the unprogrammed word lines of the block. The already programmed word lines and one or more optional buffer word lines may be inhibited from erasing during the erase operation. After erasing the unprogrammed word lines, the system completes the programming request by programming the remaining user data in the unprogrammed region of the block.
-
公开(公告)号：EP3196885A1
公开(公告)日：2017-07-26
申请号：EP16201335.3
申请日：2016-11-30
发明人： Lai, Tsung-Mu , Ching, Wen-Hao , Po, Chen-Hao
IPC分类号： G11C16/04 , H01L27/11558 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/16 , H01L23/528
CPC分类号： G11C16/30 , G11C7/065 , G11C7/10 , G11C7/12 , G11C7/22 , G11C8/10 , G11C16/0408 , G11C16/0433 , G11C16/0458 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/16 , G11C16/24 , G11C16/26 , H01L23/528 , H01L27/0207 , H01L27/11517 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11558 , H01L27/1203 , H01L29/0649 , H01L29/0847 , H01L29/1095 , H01L29/42328
摘要： A memory array (10) includes a plurality of memory pages (MP1 to MPM), each memory page (MP1 to MPM) includes a plurality of memory cells (100 1,1 to 100 M,N ), and each memory cell (100 1,1 to 100 M,N ) includes a floating gate module (110) including a floating gate transistor (112), a control transistor (120), and an erase transistor (130). The floating gate module (110) is disposed in a first well, the erase transistor (130) is disposed in a second well, and the control transistor (120) is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells (100 1,1 to 100 M,N ) of the plurality of memory pages (MP1 to MPM) are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions will not limit the circuit area of the memory array (10) and the circuit area can be reduced.
摘要翻译： 存储器阵列（10）包括多个存储器页（MP1到MPM），每个存储器页（MP1到MPM）包括多个存储器单元（1001,1到100M，N），并且每个存储器单元（1001,1 N）包括包括浮动栅极晶体管（112），控制晶体管（120）和擦除晶体管（130）的浮动栅极模块（110）。 浮置栅极模块（110）设置在第一阱中，擦除晶体管（130）设置在第二阱中，并且控制晶体管（120）设置在第三阱中。 所述第一阱，所述第二阱和所述第三阱设置在深掺杂区，所述多个存储页（MP1〜MPM）中的存储单元（1001,1〜100M，N）全部位于所述深掺杂区 。 因此，深掺杂区之间的间隔规则不会限制存储器阵列（10）的电路面积，并且可以减小电路面积。
-
公开(公告)号：EP3182415A1
公开(公告)日：2017-06-21
申请号：EP14899852.9
申请日：2014-08-14
发明人： KASHIHARA, Yoji
CPC分类号： G11C16/24 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/14 , G11C16/3427
摘要： A semiconductor device includes a first memory mat (1L) including a plurality of split type memory cells (250L), a second memory mat (1R) including a plurality of split type memory cells (250R), a first control gate line (CGL) connected to a control gate (CG) of a split type memory cell (100L), and a second control gate line (CGR) connected to a control gate (CG) of a split type memory cell (100R). The semiconductor device further includes a first memory gate line (MGL) connected to a memory gate (MG) of the split type memory cell (100L), and a second memory gate line (MGR) connected to a memory gate (MG) of the split type memory cell (100R).
摘要翻译： 一种半导体器件包括：包括多个分离式存储器单元（250L）的第一存储器垫（1L），包括多个分离式存储器单元（250R）的第二存储器垫（1R），第一控制栅极线（CGL） 连接到分离型存储单元（100L）的控制栅极（CG），以及连接到分离型存储单元（100R）的控制栅极（CG）的第二控制栅极线（CGR）。 半导体器件还包括连接到分离式存储单元（100L）的存储器栅极（MG）的第一存储器栅极线（MGL）和连接到分离式存储器单元（100L）的存储器栅极（MG）的第二存储器栅极线 分体式存储单元（100R）。
-
公开(公告)号：EP3035337A1
公开(公告)日：2016-06-22
申请号：EP13891587.1
申请日：2013-08-15
发明人： NISHIYAMA, Takayuki
CPC分类号： G11C16/3459 , G11C16/0408 , G11C16/0425 , G11C16/0441 , G11C16/14 , G11C16/26 , G11C16/28 , G11C16/3445 , G11C16/3454
摘要： A control circuit (105) controls execution of first-stage processing for increasing a threshold voltage of both or one of a first storage element (102) and a second storage element (103) until the threshold voltage of the first storage element (102) and the second storage element (103) attains to a prescribed write verify level when a request for erase of twin cell data is received. The control circuit 105 controls execution of second-stage processing for lowering a threshold voltage of the first storage element (102) and the second storage element (103) until the threshold voltage of the first storage element (102) and the second storage element (103) attains to a prescribed erase verify level after the first-stage processing is performed.
摘要翻译： 控制电路（105）控制用于增加第一存储元件（102）和第二存储元件（103）两者或一者的阈值电压直到第一存储元件（102）的阈值电压的第一级处理的执行， 和第二存储元件（103）在接收到擦除双单元数据的请求时达到规定的写验证电平。 控制电路105控制用于降低第一存储元件（102）和第二存储元件（103）的阈值电压的第二阶段处理的执行，直到第一存储元件（102）和第二存储元件（103）的阈值电压 103）在执行第一阶段处理之后达到规定的擦除验证电平。
-
公开(公告)号：EP2745295A4
公开(公告)日：2016-02-24
申请号：EP12824349
申请日：2012-08-14
发明人： GODA AKIRA , AHMED SAFQAT , HASNAT KHALED , PARAT KRISHNA K
CPC分类号： G11C16/0483 , G11C16/0408 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3418 , G11C16/3427 , H01L27/11519 , H01L27/11556 , H01L27/11565 , H01L27/11582
摘要： Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.
-
公开(公告)号：EP2941773A1
公开(公告)日：2015-11-11
申请号：EP13821341.8
申请日：2013-12-20
发明人： OOWADA, Ken , DUTTA, Deepanshu
CPC分类号： G11C16/14 , G11C11/5635 , G11C16/0483 , G11C16/3418
摘要： Techniques are disclosed herein for erasing non-volatile storage elements. A sequence of increasing erase voltages may be applied to a substrate. The select line may be floated and many of the word lines may be held at a low voltage (e.g., close to OV). However, the voltage applied to an edge word may be increased in magnitude relative to a previous voltage applied to the edge word line for at least a portion of the sequence of erase voltages. The edge word line could be the word line that is immediately adjacent to the select line. The increasing voltage applied to the edge word line may prevent or reduce damage to oxides between the select line and edge word line. It may also help to regulate the e-field across a tunnel oxide of memory cells on the edge word line.
-
公开(公告)号：EP2586060A4
公开(公告)日：2015-08-12
申请号：EP11807258
申请日：2011-06-24
发明人： TANG SANH D , ZAHURAK JOHN K
IPC分类号： H01L27/115 , H01L21/28 , H01L21/8247 , H01L27/06 , H01L27/24 , H01L29/66 , H01L29/788 , H01L29/792 , H01L45/00
CPC分类号： H01L27/11582 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C16/10 , G11C16/14 , G11C16/26 , G11C2213/71 , H01L21/28273 , H01L21/76838 , H01L23/528 , H01L27/0688 , H01L27/11519 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/11575 , H01L27/11578 , H01L27/2454 , H01L27/249 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926 , H01L45/06
摘要： Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.
-
10.发明公开Dual-mode transistor devices and methods for operating same 有权Transistorvorrichtungen mit Zweifachmodus und Verfahren zu seinem Betrieb
公开(公告)号：EP2811527A2
公开(公告)日：2014-12-10
申请号：EP14153020.4
申请日：2014-01-29
发明人： Lue, Hang-Ting , Chen, Wei-Chen
IPC分类号： H01L29/739 , H01L29/423
CPC分类号： H01L29/78645 , G11C16/0483 , G11C16/12 , G11C16/14 , G11C16/26 , H01L27/092 , H01L27/11568 , H01L29/4232 , H01L29/66484 , H01L29/7391
摘要： A dual-mode transistor structure comprises a semiconductor body. The semiconductor body of the device includes a channel region, a p-type terminal region (operable as a source or drain) adjacent a first side of the channel region and an n-type terminal region (operable as a source or drain) adjacent a second side of the channel region. A gate insulator is disposed on a surface of the semiconductor body over the channel region. A gate is disposed on the gate insulator over the channel region. A first assist gate is disposed on a first side of the gate, and a second assist gate is disposed on a second side of the gate. Optionally, a back gate can be included beneath the channel region. Biasing the assist gates can be used to select n-channel or p-channel modes in a single device.
摘要翻译： 双模式晶体管结构包括半导体本体。 器件的半导体本体包括与沟道区的第一侧相邻的沟道区，p型端子区（可作为源极或漏极），以及邻近沟道区的n型端子区域（可用作源极或漏极） 通道区域的第二侧。 栅极绝缘体设置在沟道区域上的半导体本体的表面上。 栅极设置在沟道区域上的栅极绝缘体上。 第一辅助栅极设置在栅极的第一侧上，第二辅助栅极设置在栅极的第二侧上。 可选地，可以在通道区域下方包括背栅。 可以使用偏置辅助门来在单个设备中选择n通道或p通道模式。
-
-
-
-
-
-
-
-
-
搜索结果
312 条记录 (耗时 0.025 秒)
